i2c: New PMC MSP71xx TWI bus driver
Add TWI driver for the PMC-Sierra MSP71xx devices. [JD: Drop the probe hack, don't set algo_data as we never use it, return the right error code if the driver registration fails.] Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
This commit is contained in:
Marc St-Jean
Jean Delvare
parent
c6e16295b7
commit
1b144df1d7
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@ -652,4 +652,13 @@ config I2C_PNX
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This driver can also be built as a module. If so, the module
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will be called i2c-pnx.
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config I2C_PMCMSP
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tristate "PMC MSP I2C TWI Controller"
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depends on PMC_MSP
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help
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This driver supports the PMC TWI controller on MSP devices.
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This driver can also be built as module. If so, the module
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will be called i2c-pmcmsp.
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endmenu
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@ -32,6 +32,7 @@ obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o
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obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
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obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
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obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o
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obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o
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obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
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obj-$(CONFIG_I2C_PROSAVAGE) += i2c-prosavage.o
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obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
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@ -0,0 +1,653 @@
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/*
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* Specific bus support for PMC-TWI compliant implementation on MSP71xx.
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*
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* Copyright 2005-2007 PMC-Sierra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/completion.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#define DRV_NAME "pmcmsptwi"
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#define MSP_TWI_SF_CLK_REG_OFFSET 0x00
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#define MSP_TWI_HS_CLK_REG_OFFSET 0x04
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#define MSP_TWI_CFG_REG_OFFSET 0x08
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#define MSP_TWI_CMD_REG_OFFSET 0x0c
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#define MSP_TWI_ADD_REG_OFFSET 0x10
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#define MSP_TWI_DAT_0_REG_OFFSET 0x14
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#define MSP_TWI_DAT_1_REG_OFFSET 0x18
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#define MSP_TWI_INT_STS_REG_OFFSET 0x1c
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#define MSP_TWI_INT_MSK_REG_OFFSET 0x20
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#define MSP_TWI_BUSY_REG_OFFSET 0x24
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#define MSP_TWI_INT_STS_DONE (1 << 0)
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#define MSP_TWI_INT_STS_LOST_ARBITRATION (1 << 1)
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#define MSP_TWI_INT_STS_NO_RESPONSE (1 << 2)
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#define MSP_TWI_INT_STS_DATA_COLLISION (1 << 3)
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#define MSP_TWI_INT_STS_BUSY (1 << 4)
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#define MSP_TWI_INT_STS_ALL 0x1f
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#define MSP_MAX_BYTES_PER_RW 8
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#define MSP_MAX_POLL 5
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#define MSP_POLL_DELAY 10
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#define MSP_IRQ_TIMEOUT (MSP_MAX_POLL * MSP_POLL_DELAY)
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/* IO Operation macros */
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#define pmcmsptwi_readl __raw_readl
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#define pmcmsptwi_writel __raw_writel
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/* TWI command type */
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enum pmcmsptwi_cmd_type {
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MSP_TWI_CMD_WRITE = 0, /* Write only */
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MSP_TWI_CMD_READ = 1, /* Read only */
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MSP_TWI_CMD_WRITE_READ = 2, /* Write then Read */
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};
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/* The possible results of the xferCmd */
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enum pmcmsptwi_xfer_result {
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MSP_TWI_XFER_OK = 0,
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MSP_TWI_XFER_TIMEOUT,
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MSP_TWI_XFER_BUSY,
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MSP_TWI_XFER_DATA_COLLISION,
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MSP_TWI_XFER_NO_RESPONSE,
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MSP_TWI_XFER_LOST_ARBITRATION,
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};
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/* Corresponds to a PMCTWI clock configuration register */
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struct pmcmsptwi_clock {
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u8 filter; /* Bits 15:12, default = 0x03 */
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u16 clock; /* Bits 9:0, default = 0x001f */
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};
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struct pmcmsptwi_clockcfg {
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struct pmcmsptwi_clock standard; /* The standard/fast clock config */
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struct pmcmsptwi_clock highspeed; /* The highspeed clock config */
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};
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/* Corresponds to the main TWI configuration register */
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struct pmcmsptwi_cfg {
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u8 arbf; /* Bits 15:12, default=0x03 */
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u8 nak; /* Bits 11:8, default=0x03 */
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u8 add10; /* Bit 7, default=0x00 */
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u8 mst_code; /* Bits 6:4, default=0x00 */
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u8 arb; /* Bit 1, default=0x01 */
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u8 highspeed; /* Bit 0, default=0x00 */
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};
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/* A single pmctwi command to issue */
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struct pmcmsptwi_cmd {
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u16 addr; /* The slave address (7 or 10 bits) */
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enum pmcmsptwi_cmd_type type; /* The command type */
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u8 write_len; /* Number of bytes in the write buffer */
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u8 read_len; /* Number of bytes in the read buffer */
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u8 *write_data; /* Buffer of characters to send */
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u8 *read_data; /* Buffer to fill with incoming data */
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};
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/* The private data */
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struct pmcmsptwi_data {
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void __iomem *iobase; /* iomapped base for IO */
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int irq; /* IRQ to use (0 disables) */
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struct completion wait; /* Completion for xfer */
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struct mutex lock; /* Used for threadsafeness */
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enum pmcmsptwi_xfer_result last_result; /* result of last xfer */
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};
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/* The default settings */
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const static struct pmcmsptwi_clockcfg pmcmsptwi_defclockcfg = {
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.standard = {
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.filter = 0x3,
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.clock = 0x1f,
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},
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.highspeed = {
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.filter = 0x3,
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.clock = 0x1f,
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},
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};
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const static struct pmcmsptwi_cfg pmcmsptwi_defcfg = {
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.arbf = 0x03,
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.nak = 0x03,
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.add10 = 0x00,
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.mst_code = 0x00,
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.arb = 0x01,
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.highspeed = 0x00,
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};
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static struct pmcmsptwi_data pmcmsptwi_data;
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static struct i2c_adapter pmcmsptwi_adapter;
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/* inline helper functions */
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static inline u32 pmcmsptwi_clock_to_reg(
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const struct pmcmsptwi_clock *clock)
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{
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return ((clock->filter & 0xf) << 12) | (clock->clock & 0x03ff);
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}
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static inline void pmcmsptwi_reg_to_clock(
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u32 reg, struct pmcmsptwi_clock *clock)
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{
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clock->filter = (reg >> 12) & 0xf;
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clock->clock = reg & 0x03ff;
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}
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static inline u32 pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg *cfg)
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{
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return ((cfg->arbf & 0xf) << 12) |
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((cfg->nak & 0xf) << 8) |
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((cfg->add10 & 0x1) << 7) |
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((cfg->mst_code & 0x7) << 4) |
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((cfg->arb & 0x1) << 1) |
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(cfg->highspeed & 0x1);
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}
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static inline void pmcmsptwi_reg_to_cfg(u32 reg, struct pmcmsptwi_cfg *cfg)
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{
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cfg->arbf = (reg >> 12) & 0xf;
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cfg->nak = (reg >> 8) & 0xf;
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cfg->add10 = (reg >> 7) & 0x1;
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cfg->mst_code = (reg >> 4) & 0x7;
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cfg->arb = (reg >> 1) & 0x1;
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cfg->highspeed = reg & 0x1;
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}
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/*
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* Sets the current clock configuration
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*/
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static void pmcmsptwi_set_clock_config(const struct pmcmsptwi_clockcfg *cfg,
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struct pmcmsptwi_data *data)
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{
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mutex_lock(&data->lock);
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pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->standard),
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data->iobase + MSP_TWI_SF_CLK_REG_OFFSET);
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pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->highspeed),
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data->iobase + MSP_TWI_HS_CLK_REG_OFFSET);
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mutex_unlock(&data->lock);
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}
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/*
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* Gets the current TWI bus configuration
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*/
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static void pmcmsptwi_get_twi_config(struct pmcmsptwi_cfg *cfg,
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struct pmcmsptwi_data *data)
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{
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mutex_lock(&data->lock);
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pmcmsptwi_reg_to_cfg(pmcmsptwi_readl(
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data->iobase + MSP_TWI_CFG_REG_OFFSET), cfg);
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mutex_unlock(&data->lock);
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}
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/*
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* Sets the current TWI bus configuration
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*/
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static void pmcmsptwi_set_twi_config(const struct pmcmsptwi_cfg *cfg,
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struct pmcmsptwi_data *data)
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{
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mutex_lock(&data->lock);
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pmcmsptwi_writel(pmcmsptwi_cfg_to_reg(cfg),
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data->iobase + MSP_TWI_CFG_REG_OFFSET);
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mutex_unlock(&data->lock);
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}
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/*
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* Parses the 'int_sts' register and returns a well-defined error code
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*/
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static enum pmcmsptwi_xfer_result pmcmsptwi_get_result(u32 reg)
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{
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if (reg & MSP_TWI_INT_STS_LOST_ARBITRATION) {
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dev_dbg(&pmcmsptwi_adapter.dev,
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"Result: Lost arbitration\n");
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return MSP_TWI_XFER_LOST_ARBITRATION;
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} else if (reg & MSP_TWI_INT_STS_NO_RESPONSE) {
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dev_dbg(&pmcmsptwi_adapter.dev,
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"Result: No response\n");
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return MSP_TWI_XFER_NO_RESPONSE;
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} else if (reg & MSP_TWI_INT_STS_DATA_COLLISION) {
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dev_dbg(&pmcmsptwi_adapter.dev,
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"Result: Data collision\n");
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return MSP_TWI_XFER_DATA_COLLISION;
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} else if (reg & MSP_TWI_INT_STS_BUSY) {
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dev_dbg(&pmcmsptwi_adapter.dev,
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"Result: Bus busy\n");
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return MSP_TWI_XFER_BUSY;
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}
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dev_dbg(&pmcmsptwi_adapter.dev, "Result: Operation succeeded\n");
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return MSP_TWI_XFER_OK;
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}
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/*
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* In interrupt mode, handle the interrupt.
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* NOTE: Assumes data->lock is held.
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*/
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static irqreturn_t pmcmsptwi_interrupt(int irq, void *ptr)
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{
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struct pmcmsptwi_data *data = ptr;
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u32 reason = pmcmsptwi_readl(data->iobase +
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MSP_TWI_INT_STS_REG_OFFSET);
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pmcmsptwi_writel(reason, data->iobase + MSP_TWI_INT_STS_REG_OFFSET);
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dev_dbg(&pmcmsptwi_adapter.dev, "Got interrupt 0x%08x\n", reason);
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if (!(reason & MSP_TWI_INT_STS_DONE))
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return IRQ_NONE;
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data->last_result = pmcmsptwi_get_result(reason);
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complete(&data->wait);
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return IRQ_HANDLED;
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}
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/*
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* Probe for and register the device and return 0 if there is one.
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*/
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static int __devinit pmcmsptwi_probe(struct platform_device *pldev)
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{
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struct resource *res;
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int rc = -ENODEV;
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/* get the static platform resources */
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res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pldev->dev, "IOMEM resource not found\n");
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goto ret_err;
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}
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/* reserve the memory region */
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if (!request_mem_region(res->start, res->end - res->start + 1,
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pldev->name)) {
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dev_err(&pldev->dev,
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"Unable to get memory/io address region 0x%08x\n",
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res->start);
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rc = -EBUSY;
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goto ret_err;
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}
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/* remap the memory */
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pmcmsptwi_data.iobase = ioremap_nocache(res->start,
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res->end - res->start + 1);
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if (!pmcmsptwi_data.iobase) {
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dev_err(&pldev->dev,
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"Unable to ioremap address 0x%08x\n", res->start);
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rc = -EIO;
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goto ret_unreserve;
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}
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/* request the irq */
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pmcmsptwi_data.irq = platform_get_irq(pldev, 0);
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if (pmcmsptwi_data.irq) {
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rc = request_irq(pmcmsptwi_data.irq, &pmcmsptwi_interrupt,
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IRQF_SHARED | IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
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pldev->name, &pmcmsptwi_data);
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if (rc == 0) {
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/*
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* Enable 'DONE' interrupt only.
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*
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* If you enable all interrupts, you will get one on
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* error and another when the operation completes.
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* This way you only have to handle one interrupt,
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* but you can still check all result flags.
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*/
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pmcmsptwi_writel(MSP_TWI_INT_STS_DONE,
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pmcmsptwi_data.iobase +
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MSP_TWI_INT_MSK_REG_OFFSET);
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} else {
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dev_warn(&pldev->dev,
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"Could not assign TWI IRQ handler "
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"to irq %d (continuing with poll)\n",
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pmcmsptwi_data.irq);
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pmcmsptwi_data.irq = 0;
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}
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}
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init_completion(&pmcmsptwi_data.wait);
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mutex_init(&pmcmsptwi_data.lock);
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pmcmsptwi_set_clock_config(&pmcmsptwi_defclockcfg, &pmcmsptwi_data);
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pmcmsptwi_set_twi_config(&pmcmsptwi_defcfg, &pmcmsptwi_data);
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printk(KERN_INFO DRV_NAME ": Registering MSP71xx I2C adapter\n");
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pmcmsptwi_adapter.dev.parent = &pldev->dev;
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platform_set_drvdata(pldev, &pmcmsptwi_adapter);
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i2c_set_adapdata(&pmcmsptwi_adapter, &pmcmsptwi_data);
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rc = i2c_add_adapter(&pmcmsptwi_adapter);
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if (rc) {
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dev_err(&pldev->dev, "Unable to register I2C adapter\n");
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goto ret_unmap;
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}
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return 0;
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ret_unmap:
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platform_set_drvdata(pldev, NULL);
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if (pmcmsptwi_data.irq) {
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pmcmsptwi_writel(0,
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pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
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free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
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}
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iounmap(pmcmsptwi_data.iobase);
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ret_unreserve:
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release_mem_region(res->start, res->end - res->start + 1);
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ret_err:
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return rc;
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}
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/*
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* Release the device and return 0 if there is one.
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*/
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static int __devexit pmcmsptwi_remove(struct platform_device *pldev)
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{
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struct resource *res;
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i2c_del_adapter(&pmcmsptwi_adapter);
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platform_set_drvdata(pldev, NULL);
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if (pmcmsptwi_data.irq) {
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pmcmsptwi_writel(0,
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pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
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free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
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}
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iounmap(pmcmsptwi_data.iobase);
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res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
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release_mem_region(res->start, res->end - res->start + 1);
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return 0;
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}
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/*
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* Polls the 'busy' register until the command is complete.
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* NOTE: Assumes data->lock is held.
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*/
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static void pmcmsptwi_poll_complete(struct pmcmsptwi_data *data)
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{
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int i;
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for (i = 0; i < MSP_MAX_POLL; i++) {
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u32 val = pmcmsptwi_readl(data->iobase +
|
||||
MSP_TWI_BUSY_REG_OFFSET);
|
||||
if (val == 0) {
|
||||
u32 reason = pmcmsptwi_readl(data->iobase +
|
||||
MSP_TWI_INT_STS_REG_OFFSET);
|
||||
pmcmsptwi_writel(reason, data->iobase +
|
||||
MSP_TWI_INT_STS_REG_OFFSET);
|
||||
data->last_result = pmcmsptwi_get_result(reason);
|
||||
return;
|
||||
}
|
||||
udelay(MSP_POLL_DELAY);
|
||||
}
|
||||
|
||||
dev_dbg(&pmcmsptwi_adapter.dev, "Result: Poll timeout\n");
|
||||
data->last_result = MSP_TWI_XFER_TIMEOUT;
|
||||
}
|
||||
|
||||
/*
|
||||
* Do the transfer (low level):
|
||||
* May use interrupt-driven or polling, depending on if an IRQ is
|
||||
* presently registered.
|
||||
* NOTE: Assumes data->lock is held.
|
||||
*/
|
||||
static enum pmcmsptwi_xfer_result pmcmsptwi_do_xfer(
|
||||
u32 reg, struct pmcmsptwi_data *data)
|
||||
{
|
||||
dev_dbg(&pmcmsptwi_adapter.dev, "Writing cmd reg 0x%08x\n", reg);
|
||||
pmcmsptwi_writel(reg, data->iobase + MSP_TWI_CMD_REG_OFFSET);
|
||||
if (data->irq) {
|
||||
unsigned long timeleft = wait_for_completion_timeout(
|
||||
&data->wait, MSP_IRQ_TIMEOUT);
|
||||
if (timeleft == 0) {
|
||||
dev_dbg(&pmcmsptwi_adapter.dev,
|
||||
"Result: IRQ timeout\n");
|
||||
complete(&data->wait);
|
||||
data->last_result = MSP_TWI_XFER_TIMEOUT;
|
||||
}
|
||||
} else
|
||||
pmcmsptwi_poll_complete(data);
|
||||
|
||||
return data->last_result;
|
||||
}
|
||||
|
||||
/*
|
||||
* Helper routine, converts 'pmctwi_cmd' struct to register format
|
||||
*/
|
||||
static inline u32 pmcmsptwi_cmd_to_reg(const struct pmcmsptwi_cmd *cmd)
|
||||
{
|
||||
return ((cmd->type & 0x3) << 8) |
|
||||
(((cmd->write_len - 1) & 0x7) << 4) |
|
||||
((cmd->read_len - 1) & 0x7);
|
||||
}
|
||||
|
||||
/*
|
||||
* Do the transfer (high level)
|
||||
*/
|
||||
static enum pmcmsptwi_xfer_result pmcmsptwi_xfer_cmd(
|
||||
struct pmcmsptwi_cmd *cmd,
|
||||
struct pmcmsptwi_data *data)
|
||||
{
|
||||
enum pmcmsptwi_xfer_result retval;
|
||||
|
||||
if ((cmd->type == MSP_TWI_CMD_WRITE && cmd->write_len == 0) ||
|
||||
(cmd->type == MSP_TWI_CMD_READ && cmd->read_len == 0) ||
|
||||
(cmd->type == MSP_TWI_CMD_WRITE_READ &&
|
||||
(cmd->read_len == 0 || cmd->write_len == 0))) {
|
||||
dev_err(&pmcmsptwi_adapter.dev,
|
||||
"%s: Cannot transfer less than 1 byte\n",
|
||||
__FUNCTION__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (cmd->read_len > MSP_MAX_BYTES_PER_RW ||
|
||||
cmd->write_len > MSP_MAX_BYTES_PER_RW) {
|
||||
dev_err(&pmcmsptwi_adapter.dev,
|
||||
"%s: Cannot transfer more than %d bytes\n",
|
||||
__FUNCTION__, MSP_MAX_BYTES_PER_RW);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mutex_lock(&data->lock);
|
||||
dev_dbg(&pmcmsptwi_adapter.dev,
|
||||
"Setting address to 0x%04x\n", cmd->addr);
|
||||
pmcmsptwi_writel(cmd->addr, data->iobase + MSP_TWI_ADD_REG_OFFSET);
|
||||
|
||||
if (cmd->type == MSP_TWI_CMD_WRITE ||
|
||||
cmd->type == MSP_TWI_CMD_WRITE_READ) {
|
||||
__be64 tmp = cpu_to_be64p((u64 *)cmd->write_data);
|
||||
tmp >>= (MSP_MAX_BYTES_PER_RW - cmd->write_len) * 8;
|
||||
dev_dbg(&pmcmsptwi_adapter.dev, "Writing 0x%016llx\n", tmp);
|
||||
pmcmsptwi_writel(tmp & 0x00000000ffffffffLL,
|
||||
data->iobase + MSP_TWI_DAT_0_REG_OFFSET);
|
||||
if (cmd->write_len > 4)
|
||||
pmcmsptwi_writel(tmp >> 32,
|
||||
data->iobase + MSP_TWI_DAT_1_REG_OFFSET);
|
||||
}
|
||||
|
||||
retval = pmcmsptwi_do_xfer(pmcmsptwi_cmd_to_reg(cmd), data);
|
||||
if (retval != MSP_TWI_XFER_OK)
|
||||
goto xfer_err;
|
||||
|
||||
if (cmd->type == MSP_TWI_CMD_READ ||
|
||||
cmd->type == MSP_TWI_CMD_WRITE_READ) {
|
||||
int i;
|
||||
u64 rmsk = ~(0xffffffffffffffffLL << (cmd->read_len * 8));
|
||||
u64 tmp = (u64)pmcmsptwi_readl(data->iobase +
|
||||
MSP_TWI_DAT_0_REG_OFFSET);
|
||||
if (cmd->read_len > 4)
|
||||
tmp |= (u64)pmcmsptwi_readl(data->iobase +
|
||||
MSP_TWI_DAT_1_REG_OFFSET) << 32;
|
||||
tmp &= rmsk;
|
||||
dev_dbg(&pmcmsptwi_adapter.dev, "Read 0x%016llx\n", tmp);
|
||||
|
||||
for (i = 0; i < cmd->read_len; i++)
|
||||
cmd->read_data[i] = tmp >> i;
|
||||
}
|
||||
|
||||
xfer_err:
|
||||
mutex_unlock(&data->lock);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* -- Algorithm functions -- */
|
||||
|
||||
/*
|
||||
* Sends an i2c command out on the adapter
|
||||
*/
|
||||
static int pmcmsptwi_master_xfer(struct i2c_adapter *adap,
|
||||
struct i2c_msg *msg, int num)
|
||||
{
|
||||
struct pmcmsptwi_data *data = i2c_get_adapdata(adap);
|
||||
struct pmcmsptwi_cmd cmd;
|
||||
struct pmcmsptwi_cfg oldcfg, newcfg;
|
||||
int ret;
|
||||
|
||||
if (num > 2) {
|
||||
dev_dbg(&adap->dev, "%d messages unsupported\n", num);
|
||||
return -EINVAL;
|
||||
} else if (num == 2) {
|
||||
/* Check for a dual write-then-read command */
|
||||
struct i2c_msg *nextmsg = msg + 1;
|
||||
if (!(msg->flags & I2C_M_RD) &&
|
||||
(nextmsg->flags & I2C_M_RD) &&
|
||||
msg->addr == nextmsg->addr) {
|
||||
cmd.type = MSP_TWI_CMD_WRITE_READ;
|
||||
cmd.write_len = msg->len;
|
||||
cmd.write_data = msg->buf;
|
||||
cmd.read_len = nextmsg->len;
|
||||
cmd.read_data = nextmsg->buf;
|
||||
} else {
|
||||
dev_dbg(&adap->dev,
|
||||
"Non write-read dual messages unsupported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
} else if (msg->flags & I2C_M_RD) {
|
||||
cmd.type = MSP_TWI_CMD_READ;
|
||||
cmd.read_len = msg->len;
|
||||
cmd.read_data = msg->buf;
|
||||
cmd.write_len = 0;
|
||||
cmd.write_data = NULL;
|
||||
} else {
|
||||
cmd.type = MSP_TWI_CMD_WRITE;
|
||||
cmd.read_len = 0;
|
||||
cmd.read_data = NULL;
|
||||
cmd.write_len = msg->len;
|
||||
cmd.write_data = msg->buf;
|
||||
}
|
||||
|
||||
if (msg->len == 0) {
|
||||
dev_err(&adap->dev, "Zero-byte messages unsupported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
cmd.addr = msg->addr;
|
||||
|
||||
if (msg->flags & I2C_M_TEN) {
|
||||
pmcmsptwi_get_twi_config(&newcfg, data);
|
||||
memcpy(&oldcfg, &newcfg, sizeof(oldcfg));
|
||||
|
||||
/* Set the special 10-bit address flag */
|
||||
newcfg.add10 = 1;
|
||||
|
||||
pmcmsptwi_set_twi_config(&newcfg, data);
|
||||
}
|
||||
|
||||
/* Execute the command */
|
||||
ret = pmcmsptwi_xfer_cmd(&cmd, data);
|
||||
|
||||
if (msg->flags & I2C_M_TEN)
|
||||
pmcmsptwi_set_twi_config(&oldcfg, data);
|
||||
|
||||
dev_dbg(&adap->dev, "I2C %s of %d bytes ",
|
||||
(msg->flags & I2C_M_RD) ? "read" : "write", msg->len);
|
||||
if (ret != MSP_TWI_XFER_OK) {
|
||||
/*
|
||||
* TODO: We could potentially loop and retry in the case
|
||||
* of MSP_TWI_XFER_TIMEOUT.
|
||||
*/
|
||||
dev_dbg(&adap->dev, "failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
dev_dbg(&adap->dev, "succeeded\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 pmcmsptwi_i2c_func(struct i2c_adapter *adapter)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
|
||||
I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
|
||||
I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL;
|
||||
}
|
||||
|
||||
/* -- Initialization -- */
|
||||
|
||||
static struct i2c_algorithm pmcmsptwi_algo = {
|
||||
.master_xfer = pmcmsptwi_master_xfer,
|
||||
.functionality = pmcmsptwi_i2c_func,
|
||||
};
|
||||
|
||||
static struct i2c_adapter pmcmsptwi_adapter = {
|
||||
.owner = THIS_MODULE,
|
||||
.class = I2C_CLASS_HWMON,
|
||||
.algo = &pmcmsptwi_algo,
|
||||
.name = DRV_NAME,
|
||||
};
|
||||
|
||||
static struct platform_driver pmcmsptwi_driver = {
|
||||
.probe = pmcmsptwi_probe,
|
||||
.remove = __devexit_p(pmcmsptwi_remove),
|
||||
.driver {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init pmcmsptwi_init(void)
|
||||
{
|
||||
return platform_driver_register(&pmcmsptwi_driver);
|
||||
}
|
||||
|
||||
static void __exit pmcmsptwi_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&pmcmsptwi_driver);
|
||||
}
|
||||
|
||||
MODULE_DESCRIPTION("PMC MSP TWI/SMBus/I2C driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
module_init(pmcmsptwi_init);
|
||||
module_exit(pmcmsptwi_exit);
|
||||
Loading…
Reference in New Issue