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media: ti-vpe: cal: add cal_ctx_wr_dma_enable and fix a race 

I have not noticed any errors due to this, but the DMA configuration
looks racy. Setting the DMA mode bitfield in CAL_WR_DMA_CTRL supposedly
enables the DMA. However, the driver currently a) continues configuring
the DMA after setting the mode, and b) enables the DMA interrupts only
after setting the mode.

This probably doesn't cause any issues as there should be no data coming
in to the DMA yet, but it's still better to fix this.

Add a new function, cal_ctx_wr_dma_enable(), to set the DMA mode field,
and call that function only after the DMA config and the irq enabling
has been done.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Tomi Valkeinen 2021-06-14 13:23:29 +02:00 committed by Mauro Carvalho Chehab
parent 8927a9f642
commit 1a7adfda34
1 changed files with 11 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/media/platform/ti-vpe/cal.c
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@ -409,8 +409,6 @@ static void cal_ctx_wr_dma_config(struct cal_ctx *ctx)
CAL_WR_DMA_CTRL_YSIZE_MASK); CAL_WR_DMA_CTRL_YSIZE_MASK);
cal_set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT, cal_set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT,
CAL_WR_DMA_CTRL_DTAG_MASK); CAL_WR_DMA_CTRL_DTAG_MASK);
cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST,
CAL_WR_DMA_CTRL_MODE_MASK);
cal_set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR, cal_set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR,
CAL_WR_DMA_CTRL_PATTERN_MASK); CAL_WR_DMA_CTRL_PATTERN_MASK);
cal_set_field(&val, 1, CAL_WR_DMA_CTRL_STALL_RD_MASK); cal_set_field(&val, 1, CAL_WR_DMA_CTRL_STALL_RD_MASK);
@ -442,6 +440,15 @@ void cal_ctx_set_dma_addr(struct cal_ctx *ctx, dma_addr_t addr)
cal_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->dma_ctx), addr); cal_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->dma_ctx), addr);
} }
static void cal_ctx_wr_dma_enable(struct cal_ctx *ctx)
{
u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx));
cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST,
CAL_WR_DMA_CTRL_MODE_MASK);
cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx), val);
}
static void cal_ctx_wr_dma_disable(struct cal_ctx *ctx) static void cal_ctx_wr_dma_disable(struct cal_ctx *ctx)
{ {
u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx)); u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx));
@ -500,6 +507,8 @@ void cal_ctx_start(struct cal_ctx *ctx)
CAL_HL_IRQ_WDMA_END_MASK(ctx->dma_ctx)); CAL_HL_IRQ_WDMA_END_MASK(ctx->dma_ctx));
cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(2), cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(2),
CAL_HL_IRQ_WDMA_START_MASK(ctx->dma_ctx)); CAL_HL_IRQ_WDMA_START_MASK(ctx->dma_ctx));
cal_ctx_wr_dma_enable(ctx);
} }
void cal_ctx_stop(struct cal_ctx *ctx) void cal_ctx_stop(struct cal_ctx *ctx)