Merge branch 'perf/urgent' into perf/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
commit
1a618c2cfe
4
.mailmap
4
.mailmap
|
@ -48,6 +48,9 @@ Felix Kuhling <fxkuehl@gmx.de>
|
|||
Felix Moeller <felix@derklecks.de>
|
||||
Filipe Lautert <filipe@icewall.org>
|
||||
Franck Bui-Huu <vagabon.xyz@gmail.com>
|
||||
Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com>
|
||||
Frank Rowand <frowand.list@gmail.com> <frank.rowand@am.sony.com>
|
||||
Frank Rowand <frowand.list@gmail.com> <frank.rowand@sonymobile.com>
|
||||
Frank Zago <fzago@systemfabricworks.com>
|
||||
Greg Kroah-Hartman <greg@echidna.(none)>
|
||||
Greg Kroah-Hartman <gregkh@suse.de>
|
||||
|
@ -79,6 +82,7 @@ Kay Sievers <kay.sievers@vrfy.org>
|
|||
Kenneth W Chen <kenneth.w.chen@intel.com>
|
||||
Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
|
||||
Koushik <raghavendra.koushik@neterion.com>
|
||||
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
|
||||
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
Leonid I Ananiev <leonid.i.ananiev@intel.com>
|
||||
Linas Vepstas <linas@austin.ibm.com>
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
The ARC HS can be configured with a pipeline performance monitor for counting
|
||||
CPU and cache events like cache misses and hits. Like conventional PCT there
|
||||
are 100+ hardware conditions dynamically mapped to upto 32 counters.
|
||||
are 100+ hardware conditions dynamically mapped to up to 32 counters.
|
||||
It also supports overflow interrupts.
|
||||
|
||||
Required properties:
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
The ARC700 can be configured with a pipeline performance monitor for counting
|
||||
CPU and cache events like cache misses and hits. Like conventional PCT there
|
||||
are 100+ hardware conditions dynamically mapped to upto 32 counters
|
||||
are 100+ hardware conditions dynamically mapped to up to 32 counters
|
||||
|
||||
Note that:
|
||||
* The ARC 700 PCT does not support interrupts; although HW events may be
|
||||
|
|
|
@ -192,7 +192,6 @@ nodes to be present and contain the properties described below.
|
|||
can be one of:
|
||||
"allwinner,sun6i-a31"
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"allwinner,sun8i-a23"
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||||
"arm,psci"
|
||||
"arm,realview-smp"
|
||||
"brcm,bcm-nsp-smp"
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||||
"brcm,brahma-b15"
|
||||
|
|
|
@ -6,8 +6,8 @@ RK3xxx SoCs.
|
|||
Required properties :
|
||||
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c" or
|
||||
"rockchip,rk3288-i2c".
|
||||
- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c",
|
||||
"rockchip,rk3228-i2c" or "rockchip,rk3288-i2c".
|
||||
- interrupts : interrupt number
|
||||
- clocks : parent clock
|
||||
|
||||
|
|
|
@ -9,7 +9,8 @@ have dual GMAC each represented by a child node..
|
|||
Required properties:
|
||||
- compatible: Should be "mediatek,mt7623-eth"
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupts: Should contain the frame engines interrupt
|
||||
- interrupts: Should contain the three frame engines interrupts in numeric
|
||||
order. These are fe_int0, fe_int1 and fe_int2.
|
||||
- clocks: the clock used by the core
|
||||
- clock-names: the names of the clock listed in the clocks property. These are
|
||||
"ethif", "esw", "gp2", "gp1"
|
||||
|
@ -42,7 +43,9 @@ eth: ethernet@1b100000 {
|
|||
<ðsys CLK_ETHSYS_GP2>,
|
||||
<ðsys CLK_ETHSYS_GP1>;
|
||||
clock-names = "ethif", "esw", "gp2", "gp1";
|
||||
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
|
||||
GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
|
||||
GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||
resets = <ðsys MT2701_ETHSYS_ETH_RST>;
|
||||
reset-names = "eth";
|
||||
|
|
|
@ -8,15 +8,19 @@ Required properties:
|
|||
of memory mapped region.
|
||||
- clock-names: from common clock binding:
|
||||
Required elements: "24m"
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
- #phy-cells : from the generic PHY bindings, must be 0;
|
||||
|
||||
Example:
|
||||
|
||||
edp_phy: edp-phy {
|
||||
compatible = "rockchip,rk3288-dp-phy";
|
||||
rockchip,grf = <&grf>;
|
||||
clocks = <&cru SCLK_EDP_24M>;
|
||||
clock-names = "24m";
|
||||
#phy-cells = <0>;
|
||||
grf: syscon@ff770000 {
|
||||
compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
|
||||
|
||||
...
|
||||
|
||||
edp_phy: edp-phy {
|
||||
compatible = "rockchip,rk3288-dp-phy";
|
||||
clocks = <&cru SCLK_EDP_24M>;
|
||||
clock-names = "24m";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -3,17 +3,23 @@ Rockchip EMMC PHY
|
|||
|
||||
Required properties:
|
||||
- compatible: rockchip,rk3399-emmc-phy
|
||||
- rockchip,grf : phandle to the syscon managing the "general
|
||||
register files"
|
||||
- #phy-cells: must be 0
|
||||
- reg: PHY configure reg address offset in "general
|
||||
- reg: PHY register address offset and length in "general
|
||||
register files"
|
||||
|
||||
Example:
|
||||
|
||||
emmcphy: phy {
|
||||
compatible = "rockchip,rk3399-emmc-phy";
|
||||
rockchip,grf = <&grf>;
|
||||
reg = <0xf780>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
grf: syscon@ff770000 {
|
||||
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
...
|
||||
|
||||
emmcphy: phy@f780 {
|
||||
compatible = "rockchip,rk3399-emmc-phy";
|
||||
reg = <0xf780 0x20>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -15,9 +15,10 @@ Required properties:
|
|||
is the rtc tick interrupt. The number of cells representing a interrupt
|
||||
depends on the parent interrupt controller.
|
||||
- clocks: Must contain a list of phandle and clock specifier for the rtc
|
||||
and source clocks.
|
||||
- clock-names: Must contain "rtc" and "rtc_src" entries sorted in the
|
||||
same order as the clocks property.
|
||||
clock and in the case of a s3c6410 compatible controller, also
|
||||
a source clock.
|
||||
- clock-names: Must contain "rtc" and for a s3c6410 compatible controller,
|
||||
a "rtc_src" sorted in the same order as the clocks property.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
@ -173,6 +173,10 @@ A few EV_ABS codes have special meanings:
|
|||
proximity of the device and while the value of the BTN_TOUCH code is 0. If
|
||||
the input device may be used freely in three dimensions, consider ABS_Z
|
||||
instead.
|
||||
- BTN_TOOL_<name> should be set to 1 when the tool comes into detectable
|
||||
proximity and set to 0 when the tool leaves detectable proximity.
|
||||
BTN_TOOL_<name> signals the type of tool that is currently detected by the
|
||||
hardware and is otherwise independent of ABS_DISTANCE and/or BTN_TOUCH.
|
||||
|
||||
* ABS_MT_<name>:
|
||||
- Used to describe multitouch input events. Please see
|
||||
|
|
|
@ -581,15 +581,16 @@ Specify "[Nn]ode" for node order
|
|||
"Zone Order" orders the zonelists by zone type, then by node within each
|
||||
zone. Specify "[Zz]one" for zone order.
|
||||
|
||||
Specify "[Dd]efault" to request automatic configuration. Autoconfiguration
|
||||
will select "node" order in following case.
|
||||
(1) if the DMA zone does not exist or
|
||||
(2) if the DMA zone comprises greater than 50% of the available memory or
|
||||
(3) if any node's DMA zone comprises greater than 70% of its local memory and
|
||||
the amount of local memory is big enough.
|
||||
Specify "[Dd]efault" to request automatic configuration.
|
||||
|
||||
Otherwise, "zone" order will be selected. Default order is recommended unless
|
||||
this is causing problems for your system/application.
|
||||
On 32-bit, the Normal zone needs to be preserved for allocations accessible
|
||||
by the kernel, so "zone" order will be selected.
|
||||
|
||||
On 64-bit, devices that require DMA32/DMA are relatively rare, so "node"
|
||||
order will be selected.
|
||||
|
||||
Default order is recommended unless this is causing problems for your
|
||||
system/application.
|
||||
|
||||
==============================================================
|
||||
|
||||
|
|
|
@ -19,7 +19,7 @@ ffffff0000000000 - ffffff7fffffffff (=39 bits) %esp fixup stacks
|
|||
ffffffef00000000 - ffffffff00000000 (=64 GB) EFI region mapping space
|
||||
... unused hole ...
|
||||
ffffffff80000000 - ffffffffa0000000 (=512 MB) kernel text mapping, from phys 0
|
||||
ffffffffa0000000 - ffffffffff5fffff (=1525 MB) module mapping space
|
||||
ffffffffa0000000 - ffffffffff5fffff (=1526 MB) module mapping space
|
||||
ffffffffff600000 - ffffffffffdfffff (=8 MB) vsyscalls
|
||||
ffffffffffe00000 - ffffffffffffffff (=2 MB) unused hole
|
||||
|
||||
|
@ -31,8 +31,8 @@ vmalloc space is lazily synchronized into the different PML4 pages of
|
|||
the processes using the page fault handler, with init_level4_pgt as
|
||||
reference.
|
||||
|
||||
Current X86-64 implementations only support 40 bits of address space,
|
||||
but we support up to 46 bits. This expands into MBZ space in the page tables.
|
||||
Current X86-64 implementations support up to 46 bits of address space (64 TB),
|
||||
which is our current limit. This expands into MBZ space in the page tables.
|
||||
|
||||
We map EFI runtime services in the 'efi_pgd' PGD in a 64Gb large virtual
|
||||
memory window (this size is arbitrary, it can be raised later if needed).
|
||||
|
|
15
MAINTAINERS
15
MAINTAINERS
|
@ -6027,7 +6027,7 @@ F: include/scsi/*iscsi*
|
|||
|
||||
ISCSI EXTENSIONS FOR RDMA (ISER) INITIATOR
|
||||
M: Or Gerlitz <ogerlitz@mellanox.com>
|
||||
M: Sagi Grimberg <sagig@mellanox.com>
|
||||
M: Sagi Grimberg <sagi@grimberg.me>
|
||||
M: Roi Dayan <roid@mellanox.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Supported
|
||||
|
@ -6037,7 +6037,7 @@ Q: http://patchwork.kernel.org/project/linux-rdma/list/
|
|||
F: drivers/infiniband/ulp/iser/
|
||||
|
||||
ISCSI EXTENSIONS FOR RDMA (ISER) TARGET
|
||||
M: Sagi Grimberg <sagig@mellanox.com>
|
||||
M: Sagi Grimberg <sagi@grimberg.me>
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending.git master
|
||||
L: linux-rdma@vger.kernel.org
|
||||
L: target-devel@vger.kernel.org
|
||||
|
@ -6400,7 +6400,7 @@ F: mm/kmemleak.c
|
|||
F: mm/kmemleak-test.c
|
||||
|
||||
KPROBES
|
||||
M: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
|
||||
M: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com>
|
||||
M: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
|
||||
M: "David S. Miller" <davem@davemloft.net>
|
||||
M: Masami Hiramatsu <mhiramat@kernel.org>
|
||||
|
@ -11071,6 +11071,15 @@ S: Maintained
|
|||
F: drivers/clk/ti/
|
||||
F: include/linux/clk/ti.h
|
||||
|
||||
TI ETHERNET SWITCH DRIVER (CPSW)
|
||||
M: Mugunthan V N <mugunthanvnm@ti.com>
|
||||
R: Grygorii Strashko <grygorii.strashko@ti.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/ti/cpsw*
|
||||
F: drivers/net/ethernet/ti/davinci*
|
||||
|
||||
TI FLASH MEDIA INTERFACE DRIVER
|
||||
M: Alex Dubov <oakad@yahoo.com>
|
||||
S: Maintained
|
||||
|
|
7
Makefile
7
Makefile
|
@ -1,8 +1,8 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc4
|
||||
NAME = Blurry Fish Butt
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Charred Weasel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
# To see a list of typical targets execute "make help"
|
||||
|
@ -1008,7 +1008,8 @@ prepare0: archprepare FORCE
|
|||
prepare: prepare0 prepare-objtool
|
||||
|
||||
ifdef CONFIG_STACK_VALIDATION
|
||||
has_libelf := $(shell echo "int main() {}" | $(HOSTCC) -xc -o /dev/null -lelf - &> /dev/null && echo 1 || echo 0)
|
||||
has_libelf := $(call try-run,\
|
||||
echo "int main() {}" | $(HOSTCC) -xc -o /dev/null -lelf -,1,0)
|
||||
ifeq ($(has_libelf),1)
|
||||
objtool_target := tools/objtool FORCE
|
||||
else
|
||||
|
|
|
@ -35,8 +35,10 @@ config ARC
|
|||
select NO_BOOTMEM
|
||||
select OF
|
||||
select OF_EARLY_FLATTREE
|
||||
select OF_RESERVED_MEM
|
||||
select PERF_USE_VMALLOC
|
||||
select HAVE_DEBUG_STACKOVERFLOW
|
||||
select HAVE_GENERIC_DMA_COHERENT
|
||||
|
||||
config MIGHT_HAVE_PCI
|
||||
bool
|
||||
|
|
|
@ -18,6 +18,12 @@
|
|||
#define STATUS_AD_MASK (1<<STATUS_AD_BIT)
|
||||
#define STATUS_IE_MASK (1<<STATUS_IE_BIT)
|
||||
|
||||
/* status32 Bits as encoded/expected by CLRI/SETI */
|
||||
#define CLRI_STATUS_IE_BIT 4
|
||||
|
||||
#define CLRI_STATUS_E_MASK 0xF
|
||||
#define CLRI_STATUS_IE_MASK (1 << CLRI_STATUS_IE_BIT)
|
||||
|
||||
#define AUX_USER_SP 0x00D
|
||||
#define AUX_IRQ_CTRL 0x00E
|
||||
#define AUX_IRQ_ACT 0x043 /* Active Intr across all levels */
|
||||
|
@ -100,6 +106,13 @@ static inline long arch_local_save_flags(void)
|
|||
:
|
||||
: "memory");
|
||||
|
||||
/* To be compatible with irq_save()/irq_restore()
|
||||
* encode the irq bits as expected by CLRI/SETI
|
||||
* (this was needed to make CONFIG_TRACE_IRQFLAGS work)
|
||||
*/
|
||||
temp = (1 << 5) |
|
||||
((!!(temp & STATUS_IE_MASK)) << CLRI_STATUS_IE_BIT) |
|
||||
(temp & CLRI_STATUS_E_MASK);
|
||||
return temp;
|
||||
}
|
||||
|
||||
|
@ -108,7 +121,7 @@ static inline long arch_local_save_flags(void)
|
|||
*/
|
||||
static inline int arch_irqs_disabled_flags(unsigned long flags)
|
||||
{
|
||||
return !(flags & (STATUS_IE_MASK));
|
||||
return !(flags & CLRI_STATUS_IE_MASK);
|
||||
}
|
||||
|
||||
static inline int arch_irqs_disabled(void)
|
||||
|
@ -128,11 +141,32 @@ static inline void arc_softirq_clear(int irq)
|
|||
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_TRACE_IRQFLAGS
|
||||
|
||||
.macro TRACE_ASM_IRQ_DISABLE
|
||||
bl trace_hardirqs_off
|
||||
.endm
|
||||
|
||||
.macro TRACE_ASM_IRQ_ENABLE
|
||||
bl trace_hardirqs_on
|
||||
.endm
|
||||
|
||||
#else
|
||||
|
||||
.macro TRACE_ASM_IRQ_DISABLE
|
||||
.endm
|
||||
|
||||
.macro TRACE_ASM_IRQ_ENABLE
|
||||
.endm
|
||||
|
||||
#endif
|
||||
.macro IRQ_DISABLE scratch
|
||||
clri
|
||||
TRACE_ASM_IRQ_DISABLE
|
||||
.endm
|
||||
|
||||
.macro IRQ_ENABLE scratch
|
||||
TRACE_ASM_IRQ_ENABLE
|
||||
seti
|
||||
.endm
|
||||
|
||||
|
|
|
@ -69,8 +69,11 @@ ENTRY(handle_interrupt)
|
|||
|
||||
clri ; To make status32.IE agree with CPU internal state
|
||||
|
||||
lr r0, [ICAUSE]
|
||||
#ifdef CONFIG_TRACE_IRQFLAGS
|
||||
TRACE_ASM_IRQ_DISABLE
|
||||
#endif
|
||||
|
||||
lr r0, [ICAUSE]
|
||||
mov blink, ret_from_exception
|
||||
|
||||
b.d arch_do_IRQ
|
||||
|
@ -169,6 +172,11 @@ END(EV_TLBProtV)
|
|||
|
||||
.Lrestore_regs:
|
||||
|
||||
# Interrpts are actually disabled from this point on, but will get
|
||||
# reenabled after we return from interrupt/exception.
|
||||
# But irq tracer needs to be told now...
|
||||
TRACE_ASM_IRQ_ENABLE
|
||||
|
||||
ld r0, [sp, PT_status32] ; U/K mode at time of entry
|
||||
lr r10, [AUX_IRQ_ACT]
|
||||
|
||||
|
|
|
@ -341,6 +341,9 @@ END(call_do_page_fault)
|
|||
|
||||
.Lrestore_regs:
|
||||
|
||||
# Interrpts are actually disabled from this point on, but will get
|
||||
# reenabled after we return from interrupt/exception.
|
||||
# But irq tracer needs to be told now...
|
||||
TRACE_ASM_IRQ_ENABLE
|
||||
|
||||
lr r10, [status32]
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
#include <linux/initrd.h>
|
||||
#endif
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/swap.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/highmem.h>
|
||||
|
@ -136,6 +137,9 @@ void __init setup_arch_memory(void)
|
|||
memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
|
||||
#endif
|
||||
|
||||
early_init_fdt_reserve_self();
|
||||
early_init_fdt_scan_reserved_mem();
|
||||
|
||||
memblock_dump_all();
|
||||
|
||||
/*----------------- node/zones setup --------------------------*/
|
||||
|
|
|
@ -860,7 +860,7 @@
|
|||
ti,no-idle-on-init;
|
||||
reg = <0x50000000 0x2000>;
|
||||
interrupts = <100>;
|
||||
dmas = <&edma 52>;
|
||||
dmas = <&edma 52 0>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <7>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
|
|
|
@ -884,7 +884,7 @@
|
|||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
dmas = <&edma 52>;
|
||||
dmas = <&edma 52 0>;
|
||||
dma-names = "rxtx";
|
||||
clocks = <&l3s_gclk>;
|
||||
clock-names = "fck";
|
||||
|
|
|
@ -99,13 +99,6 @@
|
|||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
extcon_usb1: extcon_usb1 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&extcon_usb1_pins>;
|
||||
};
|
||||
|
||||
hdmi0: connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
|
@ -349,12 +342,6 @@
|
|||
>;
|
||||
};
|
||||
|
||||
extcon_usb1_pins: extcon_usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
|
||||
>;
|
||||
};
|
||||
|
||||
tpd12s015_pins: pinmux_tpd12s015_pins {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
|
||||
|
@ -706,10 +693,6 @@
|
|||
pinctrl-0 = <&usb1_pins>;
|
||||
};
|
||||
|
||||
&omap_dwc3_1 {
|
||||
extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
||||
&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
|
|
@ -4,6 +4,157 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
&pllss {
|
||||
/*
|
||||
* See TRM "2.6.10 Connected outputso DPLLS" and
|
||||
* "2.6.11 Connected Outputs of DPLLJ". Only clkout is
|
||||
* connected except for hdmi and usb.
|
||||
*/
|
||||
adpll_mpu_ck: adpll@40 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-s-clock";
|
||||
reg = <0x40 0x40>;
|
||||
clocks = <&devosc_ck &devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow", "clkinphif";
|
||||
clock-output-names = "481c5040.adpll.dcoclkldo",
|
||||
"481c5040.adpll.clkout",
|
||||
"481c5040.adpll.clkoutx2",
|
||||
"481c5040.adpll.clkouthif";
|
||||
};
|
||||
|
||||
adpll_dsp_ck: adpll@80 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x80 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5080.adpll.dcoclkldo",
|
||||
"481c5080.adpll.clkout",
|
||||
"481c5080.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_sgx_ck: adpll@b0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0xb0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c50b0.adpll.dcoclkldo",
|
||||
"481c50b0.adpll.clkout",
|
||||
"481c50b0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_hdvic_ck: adpll@e0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0xe0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c50e0.adpll.dcoclkldo",
|
||||
"481c50e0.adpll.clkout",
|
||||
"481c50e0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_l3_ck: adpll@110 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x110 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5110.adpll.dcoclkldo",
|
||||
"481c5110.adpll.clkout",
|
||||
"481c5110.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_isp_ck: adpll@140 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x140 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5140.adpll.dcoclkldo",
|
||||
"481c5140.adpll.clkout",
|
||||
"481c5140.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_dss_ck: adpll@170 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x170 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5170.adpll.dcoclkldo",
|
||||
"481c5170.adpll.clkout",
|
||||
"481c5170.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_video0_ck: adpll@1a0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x1a0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c51a0.adpll.dcoclkldo",
|
||||
"481c51a0.adpll.clkout",
|
||||
"481c51a0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_video1_ck: adpll@1d0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x1d0 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c51d0.adpll.dcoclkldo",
|
||||
"481c51d0.adpll.clkout",
|
||||
"481c51d0.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_hdmi_ck: adpll@200 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x200 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5200.adpll.dcoclkldo",
|
||||
"481c5200.adpll.clkout",
|
||||
"481c5200.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_audio_ck: adpll@230 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x230 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5230.adpll.dcoclkldo",
|
||||
"481c5230.adpll.clkout",
|
||||
"481c5230.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_usb_ck: adpll@260 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x260 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5260.adpll.dcoclkldo",
|
||||
"481c5260.adpll.clkout",
|
||||
"481c5260.adpll.clkoutldo";
|
||||
};
|
||||
|
||||
adpll_ddr_ck: adpll@290 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm814-adpll-lj-clock";
|
||||
reg = <0x290 0x30>;
|
||||
clocks = <&devosc_ck &devosc_ck>;
|
||||
clock-names = "clkinp", "clkinpulow";
|
||||
clock-output-names = "481c5290.adpll.dcoclkldo",
|
||||
"481c5290.adpll.clkout",
|
||||
"481c5290.adpll.clkoutldo";
|
||||
};
|
||||
};
|
||||
|
||||
&pllss_clocks {
|
||||
timer1_fck: timer1_fck {
|
||||
#clock-cells = <0>;
|
||||
|
@ -23,6 +174,24 @@
|
|||
reg = <0x2e0>;
|
||||
};
|
||||
|
||||
/* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&adpll_video0_ck 1
|
||||
&adpll_video1_ck 1
|
||||
&adpll_audio_ck 1>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x2e8>;
|
||||
};
|
||||
|
||||
/* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
sysclk18_ck: sysclk18_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
|
@ -79,37 +248,6 @@
|
|||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
|
||||
sysclk4_ck: sysclk4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <222000000>;
|
||||
};
|
||||
|
||||
sysclk6_ck: sysclk6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
sysclk10_ck: sysclk10_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&prcm_clocks {
|
||||
|
@ -138,6 +276,49 @@
|
|||
clock-div = <78125>;
|
||||
};
|
||||
|
||||
/* L4_HS 220 MHz*/
|
||||
sysclk4_ck: sysclk4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_l3_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <1>;
|
||||
};
|
||||
|
||||
/* L4_FWCFG */
|
||||
sysclk5_ck: sysclk5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_l3_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <2>;
|
||||
};
|
||||
|
||||
/* L4_LS 110 MHz */
|
||||
sysclk6_ck: sysclk6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_l3_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <2>;
|
||||
};
|
||||
|
||||
sysclk8_ck: sysclk8_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&adpll_usb_ck 1>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <1>;
|
||||
};
|
||||
|
||||
sysclk10_ck: sysclk10_ck {
|
||||
compatible = "ti,divider-clock";
|
||||
reg = <0x324>;
|
||||
ti,max-div = <7>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&adpll_usb_ck 1>;
|
||||
};
|
||||
|
||||
aud_clkin0_ck: aud_clkin0_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
|
|
@ -6,6 +6,32 @@
|
|||
|
||||
#include "dm814x-clocks.dtsi"
|
||||
|
||||
/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
|
||||
&adpll_hdvic_ck {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&adpll_l3_ck {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&adpll_dss_ck {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
|
||||
&sysclk4_ck {
|
||||
clocks = <&adpll_isp_ck 1>;
|
||||
};
|
||||
|
||||
&sysclk5_ck {
|
||||
clocks = <&adpll_isp_ck 1>;
|
||||
};
|
||||
|
||||
&sysclk6_ck {
|
||||
clocks = <&adpll_isp_ck 1>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Compared to dm814x, dra62x has different shifts and more mux options.
|
||||
* Please add the extra options for ysclk_14 and 16 if really needed.
|
||||
|
|
|
@ -98,12 +98,20 @@
|
|||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
sys_32k_ck: sys_32k_ck {
|
||||
sys_clk32_crystal_ck: sys_clk32_crystal_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin1>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <610>;
|
||||
};
|
||||
|
||||
virt_12000000_ck: virt_12000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
@ -2170,4 +2178,12 @@
|
|||
ti,bit-shift = <22>;
|
||||
reg = <0x0558>;
|
||||
};
|
||||
|
||||
sys_32k_ck: sys_32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x6c4>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
|
@ -460,8 +460,6 @@
|
|||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
spmi_bus: spmi@fc4cf000 {
|
||||
|
@ -479,16 +477,6 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
};
|
||||
|
||||
blsp2_dma: dma-controller@f9944000 {
|
||||
compatible = "qcom,bam-v1.4.0";
|
||||
reg = <0xf9944000 0x19000>;
|
||||
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
smd {
|
||||
|
|
|
@ -661,6 +661,7 @@
|
|||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -143,19 +143,11 @@
|
|||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif0_pins: serial0 {
|
||||
renesas,groups = "scif0_data_d";
|
||||
renesas,function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
renesas,groups = "scif_clk";
|
||||
renesas,function = "scif_clk";
|
||||
};
|
||||
|
||||
ether_pins: ether {
|
||||
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
|
||||
renesas,function = "eth";
|
||||
|
@ -229,11 +221,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -414,6 +401,7 @@
|
|||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -1083,9 +1083,8 @@
|
|||
pcie_bus_clk: pcie_bus_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "pcie_bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
|
@ -1094,7 +1093,6 @@
|
|||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* External USB clock - can be overridden by the board */
|
||||
|
@ -1112,7 +1110,6 @@
|
|||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "can_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Special CPG clocks */
|
||||
|
|
|
@ -276,7 +276,7 @@ static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
|
|||
int feature = (features >> field) & 15;
|
||||
|
||||
/* feature registers are signed values */
|
||||
if (feature > 8)
|
||||
if (feature > 7)
|
||||
feature -= 16;
|
||||
|
||||
return feature;
|
||||
|
|
|
@ -512,7 +512,7 @@ static void __init elf_hwcap_fixup(void)
|
|||
*/
|
||||
if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
|
||||
(cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
|
||||
cpuid_feature_extract(CPUID_EXT_ISAR3, 20) >= 3))
|
||||
cpuid_feature_extract(CPUID_EXT_ISAR4, 20) >= 3))
|
||||
elf_hwcap &= ~HWCAP_SWP;
|
||||
}
|
||||
|
||||
|
|
|
@ -71,6 +71,7 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx(
|
|||
if (!pdata)
|
||||
pdata = &default_esdhc_pdata;
|
||||
|
||||
return imx_add_platform_device(data->devid, data->id, res,
|
||||
ARRAY_SIZE(res), pdata, sizeof(*pdata));
|
||||
return imx_add_platform_device_dmamask(data->devid, data->id, res,
|
||||
ARRAY_SIZE(res), pdata, sizeof(*pdata),
|
||||
DMA_BIT_MASK(32));
|
||||
}
|
||||
|
|
|
@ -461,7 +461,7 @@ static struct clockdomain ipu_7xx_clkdm = {
|
|||
.cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
|
||||
.clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
|
||||
.dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
||||
static struct clockdomain mpu1_7xx_clkdm = {
|
||||
|
|
|
@ -737,7 +737,8 @@ void __init omap5_init_late(void)
|
|||
#ifdef CONFIG_SOC_DRA7XX
|
||||
void __init dra7xx_init_early(void)
|
||||
{
|
||||
omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
|
||||
omap2_set_globals_tap(DRA7XX_CLASS,
|
||||
OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
|
||||
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
|
||||
omap2_control_base_init();
|
||||
omap4_pm_init_early();
|
||||
|
|
|
@ -274,6 +274,10 @@ static inline void omap5_irq_save_context(void)
|
|||
*/
|
||||
static void irq_save_context(void)
|
||||
{
|
||||
/* DRA7 has no SAR to save */
|
||||
if (soc_is_dra7xx())
|
||||
return;
|
||||
|
||||
if (!sar_base)
|
||||
sar_base = omap4_get_sar_ram_base();
|
||||
|
||||
|
@ -290,6 +294,9 @@ static void irq_sar_clear(void)
|
|||
{
|
||||
u32 val;
|
||||
u32 offset = SAR_BACKUP_STATUS_OFFSET;
|
||||
/* DRA7 has no SAR to save */
|
||||
if (soc_is_dra7xx())
|
||||
return;
|
||||
|
||||
if (soc_is_omap54xx())
|
||||
offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
|
||||
|
|
|
@ -198,7 +198,6 @@ void omap_sram_idle(void)
|
|||
int per_next_state = PWRDM_POWER_ON;
|
||||
int core_next_state = PWRDM_POWER_ON;
|
||||
int per_going_off;
|
||||
int core_prev_state;
|
||||
u32 sdrc_pwr = 0;
|
||||
|
||||
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
|
||||
|
@ -278,16 +277,20 @@ void omap_sram_idle(void)
|
|||
sdrc_write_reg(sdrc_pwr, SDRC_POWER);
|
||||
|
||||
/* CORE */
|
||||
if (core_next_state < PWRDM_POWER_ON) {
|
||||
core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
|
||||
if (core_prev_state == PWRDM_POWER_OFF) {
|
||||
omap3_core_restore_context();
|
||||
omap3_cm_restore_context();
|
||||
omap3_sram_restore_context();
|
||||
omap2_sms_restore_context();
|
||||
}
|
||||
if (core_next_state < PWRDM_POWER_ON &&
|
||||
pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
|
||||
omap3_core_restore_context();
|
||||
omap3_cm_restore_context();
|
||||
omap3_sram_restore_context();
|
||||
omap2_sms_restore_context();
|
||||
} else {
|
||||
/*
|
||||
* In off-mode resume path above, omap3_core_restore_context
|
||||
* also handles the INTC autoidle restore done here so limit
|
||||
* this to non-off mode resume paths so we don't do it twice.
|
||||
*/
|
||||
omap3_intc_resume_idle();
|
||||
}
|
||||
omap3_intc_resume_idle();
|
||||
|
||||
pwrdm_post_transition(NULL);
|
||||
|
||||
|
|
|
@ -40,8 +40,7 @@ static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
|
|||
void __init shmobile_init_delay(void)
|
||||
{
|
||||
struct device_node *np, *cpus;
|
||||
bool is_a7_a8_a9 = false;
|
||||
bool is_a15 = false;
|
||||
unsigned int div = 0;
|
||||
bool has_arch_timer = false;
|
||||
u32 max_freq = 0;
|
||||
|
||||
|
@ -55,27 +54,22 @@ void __init shmobile_init_delay(void)
|
|||
if (!of_property_read_u32(np, "clock-frequency", &freq))
|
||||
max_freq = max(max_freq, freq);
|
||||
|
||||
if (of_device_is_compatible(np, "arm,cortex-a8") ||
|
||||
of_device_is_compatible(np, "arm,cortex-a9")) {
|
||||
is_a7_a8_a9 = true;
|
||||
} else if (of_device_is_compatible(np, "arm,cortex-a7")) {
|
||||
is_a7_a8_a9 = true;
|
||||
has_arch_timer = true;
|
||||
} else if (of_device_is_compatible(np, "arm,cortex-a15")) {
|
||||
is_a15 = true;
|
||||
if (of_device_is_compatible(np, "arm,cortex-a8")) {
|
||||
div = 2;
|
||||
} else if (of_device_is_compatible(np, "arm,cortex-a9")) {
|
||||
div = 1;
|
||||
} else if (of_device_is_compatible(np, "arm,cortex-a7") ||
|
||||
of_device_is_compatible(np, "arm,cortex-a15")) {
|
||||
div = 1;
|
||||
has_arch_timer = true;
|
||||
}
|
||||
}
|
||||
|
||||
of_node_put(cpus);
|
||||
|
||||
if (!max_freq)
|
||||
if (!max_freq || !div)
|
||||
return;
|
||||
|
||||
if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
|
||||
if (is_a7_a8_a9)
|
||||
shmobile_setup_delay_hz(max_freq, 1, 3);
|
||||
else if (is_a15)
|
||||
shmobile_setup_delay_hz(max_freq, 2, 4);
|
||||
}
|
||||
if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
|
||||
shmobile_setup_delay_hz(max_freq, 1, div);
|
||||
}
|
||||
|
|
|
@ -762,7 +762,8 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
|
|||
if (!mask)
|
||||
return NULL;
|
||||
|
||||
buf = kzalloc(sizeof(*buf), gfp);
|
||||
buf = kzalloc(sizeof(*buf),
|
||||
gfp & ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM));
|
||||
if (!buf)
|
||||
return NULL;
|
||||
|
||||
|
|
|
@ -70,7 +70,6 @@
|
|||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -201,15 +201,12 @@
|
|||
|
||||
i2c2: i2c@58782000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c3: i2c@58783000 {
|
||||
|
@ -227,12 +224,15 @@
|
|||
|
||||
i2c4: i2c@58784000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58784000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 45 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c5: i2c@58785000 {
|
||||
|
@ -245,16 +245,6 @@
|
|||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c6: i2c@58786000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
system_bus: system-bus@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus";
|
||||
status = "disabled";
|
||||
|
|
|
@ -588,6 +588,15 @@ set_hcr:
|
|||
msr vpidr_el2, x0
|
||||
msr vmpidr_el2, x1
|
||||
|
||||
/*
|
||||
* When VHE is not in use, early init of EL2 and EL1 needs to be
|
||||
* done here.
|
||||
* When VHE _is_ in use, EL1 will not be used in the host and
|
||||
* requires no configuration, and all non-hyp-specific EL2 setup
|
||||
* will be done via the _EL1 system register aliases in __cpu_setup.
|
||||
*/
|
||||
cbnz x2, 1f
|
||||
|
||||
/* sctlr_el1 */
|
||||
mov x0, #0x0800 // Set/clear RES{1,0} bits
|
||||
CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
|
||||
|
@ -597,6 +606,7 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
|
|||
/* Coprocessor traps. */
|
||||
mov x0, #0x33ff
|
||||
msr cptr_el2, x0 // Disable copro. traps to EL2
|
||||
1:
|
||||
|
||||
#ifdef CONFIG_COMPAT
|
||||
msr hstr_el2, xzr // Disable CP15 traps to EL2
|
||||
|
@ -734,7 +744,8 @@ ENDPROC(__secondary_switched)
|
|||
|
||||
.macro update_early_cpu_boot_status status, tmp1, tmp2
|
||||
mov \tmp2, #\status
|
||||
str_l \tmp2, __early_cpu_boot_status, \tmp1
|
||||
adr_l \tmp1, __early_cpu_boot_status
|
||||
str \tmp2, [\tmp1]
|
||||
dmb sy
|
||||
dc ivac, \tmp1 // Invalidate potentially stale cache line
|
||||
.endm
|
||||
|
|
|
@ -52,6 +52,7 @@ static void write_pen_release(u64 val)
|
|||
static int smp_spin_table_cpu_init(unsigned int cpu)
|
||||
{
|
||||
struct device_node *dn;
|
||||
int ret;
|
||||
|
||||
dn = of_get_cpu_node(cpu, NULL);
|
||||
if (!dn)
|
||||
|
@ -60,15 +61,15 @@ static int smp_spin_table_cpu_init(unsigned int cpu)
|
|||
/*
|
||||
* Determine the address from which the CPU is polling.
|
||||
*/
|
||||
if (of_property_read_u64(dn, "cpu-release-addr",
|
||||
&cpu_release_addr[cpu])) {
|
||||
ret = of_property_read_u64(dn, "cpu-release-addr",
|
||||
&cpu_release_addr[cpu]);
|
||||
if (ret)
|
||||
pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
|
||||
cpu);
|
||||
|
||||
return -1;
|
||||
}
|
||||
of_node_put(dn);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int smp_spin_table_cpu_prepare(unsigned int cpu)
|
||||
|
|
|
@ -68,7 +68,7 @@ void *memset(void *s, int c, size_t count)
|
|||
"=r" (charcnt), /* %1 Output */
|
||||
"=r" (dwordcnt), /* %2 Output */
|
||||
"=r" (fill8reg), /* %3 Output */
|
||||
"=r" (wrkrega) /* %4 Output */
|
||||
"=&r" (wrkrega) /* %4 Output only */
|
||||
: "r" (c), /* %5 Input */
|
||||
"0" (s), /* %0 Input/Output */
|
||||
"1" (count) /* %1 Input/Output */
|
||||
|
|
|
@ -384,3 +384,5 @@ SYSCALL(ni_syscall)
|
|||
SYSCALL(ni_syscall)
|
||||
SYSCALL(mlock2)
|
||||
SYSCALL(copy_file_range)
|
||||
COMPAT_SYS_SPU(preadv2)
|
||||
COMPAT_SYS_SPU(pwritev2)
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
#include <uapi/asm/unistd.h>
|
||||
|
||||
|
||||
#define NR_syscalls 380
|
||||
#define NR_syscalls 382
|
||||
|
||||
#define __NR__exit __NR_exit
|
||||
|
||||
|
|
|
@ -31,6 +31,7 @@
|
|||
#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
|
||||
0x00000040
|
||||
|
||||
/* Reserved - do not use 0x00000004 */
|
||||
#define PPC_FEATURE_TRUE_LE 0x00000002
|
||||
#define PPC_FEATURE_PPC_LE 0x00000001
|
||||
|
||||
|
|
|
@ -390,5 +390,7 @@
|
|||
#define __NR_membarrier 365
|
||||
#define __NR_mlock2 378
|
||||
#define __NR_copy_file_range 379
|
||||
#define __NR_preadv2 380
|
||||
#define __NR_pwritev2 381
|
||||
|
||||
#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */
|
||||
|
|
|
@ -148,23 +148,25 @@ static struct ibm_pa_feature {
|
|||
unsigned long cpu_features; /* CPU_FTR_xxx bit */
|
||||
unsigned long mmu_features; /* MMU_FTR_xxx bit */
|
||||
unsigned int cpu_user_ftrs; /* PPC_FEATURE_xxx bit */
|
||||
unsigned int cpu_user_ftrs2; /* PPC_FEATURE2_xxx bit */
|
||||
unsigned char pabyte; /* byte number in ibm,pa-features */
|
||||
unsigned char pabit; /* bit number (big-endian) */
|
||||
unsigned char invert; /* if 1, pa bit set => clear feature */
|
||||
} ibm_pa_features[] __initdata = {
|
||||
{0, 0, PPC_FEATURE_HAS_MMU, 0, 0, 0},
|
||||
{0, 0, PPC_FEATURE_HAS_FPU, 0, 1, 0},
|
||||
{CPU_FTR_CTRL, 0, 0, 0, 3, 0},
|
||||
{CPU_FTR_NOEXECUTE, 0, 0, 0, 6, 0},
|
||||
{CPU_FTR_NODSISRALIGN, 0, 0, 1, 1, 1},
|
||||
{0, MMU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0},
|
||||
{CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0},
|
||||
{0, 0, PPC_FEATURE_HAS_MMU, 0, 0, 0, 0},
|
||||
{0, 0, PPC_FEATURE_HAS_FPU, 0, 0, 1, 0},
|
||||
{CPU_FTR_CTRL, 0, 0, 0, 0, 3, 0},
|
||||
{CPU_FTR_NOEXECUTE, 0, 0, 0, 0, 6, 0},
|
||||
{CPU_FTR_NODSISRALIGN, 0, 0, 0, 1, 1, 1},
|
||||
{0, MMU_FTR_CI_LARGE_PAGE, 0, 0, 1, 2, 0},
|
||||
{CPU_FTR_REAL_LE, 0, PPC_FEATURE_TRUE_LE, 0, 5, 0, 0},
|
||||
/*
|
||||
* If the kernel doesn't support TM (ie. CONFIG_PPC_TRANSACTIONAL_MEM=n),
|
||||
* we don't want to turn on CPU_FTR_TM here, so we use CPU_FTR_TM_COMP
|
||||
* which is 0 if the kernel doesn't support TM.
|
||||
* If the kernel doesn't support TM (ie CONFIG_PPC_TRANSACTIONAL_MEM=n),
|
||||
* we don't want to turn on TM here, so we use the *_COMP versions
|
||||
* which are 0 if the kernel doesn't support TM.
|
||||
*/
|
||||
{CPU_FTR_TM_COMP, 0, 0, 22, 0, 0},
|
||||
{CPU_FTR_TM_COMP, 0, 0,
|
||||
PPC_FEATURE2_HTM_COMP|PPC_FEATURE2_HTM_NOSC_COMP, 22, 0, 0},
|
||||
};
|
||||
|
||||
static void __init scan_features(unsigned long node, const unsigned char *ftrs,
|
||||
|
@ -195,10 +197,12 @@ static void __init scan_features(unsigned long node, const unsigned char *ftrs,
|
|||
if (bit ^ fp->invert) {
|
||||
cur_cpu_spec->cpu_features |= fp->cpu_features;
|
||||
cur_cpu_spec->cpu_user_features |= fp->cpu_user_ftrs;
|
||||
cur_cpu_spec->cpu_user_features2 |= fp->cpu_user_ftrs2;
|
||||
cur_cpu_spec->mmu_features |= fp->mmu_features;
|
||||
} else {
|
||||
cur_cpu_spec->cpu_features &= ~fp->cpu_features;
|
||||
cur_cpu_spec->cpu_user_features &= ~fp->cpu_user_ftrs;
|
||||
cur_cpu_spec->cpu_user_features2 &= ~fp->cpu_user_ftrs2;
|
||||
cur_cpu_spec->mmu_features &= ~fp->mmu_features;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -4,6 +4,9 @@ config MMU
|
|||
config ZONE_DMA
|
||||
def_bool y
|
||||
|
||||
config CPU_BIG_ENDIAN
|
||||
def_bool y
|
||||
|
||||
config LOCKDEP_SUPPORT
|
||||
def_bool y
|
||||
|
||||
|
|
|
@ -11,7 +11,7 @@ typedef struct {
|
|||
spinlock_t list_lock;
|
||||
struct list_head pgtable_list;
|
||||
struct list_head gmap_list;
|
||||
unsigned long asce_bits;
|
||||
unsigned long asce;
|
||||
unsigned long asce_limit;
|
||||
unsigned long vdso_base;
|
||||
/* The mmu context allocates 4K page tables. */
|
||||
|
|
|
@ -26,12 +26,28 @@ static inline int init_new_context(struct task_struct *tsk,
|
|||
mm->context.has_pgste = 0;
|
||||
mm->context.use_skey = 0;
|
||||
#endif
|
||||
if (mm->context.asce_limit == 0) {
|
||||
switch (mm->context.asce_limit) {
|
||||
case 1UL << 42:
|
||||
/*
|
||||
* forked 3-level task, fall through to set new asce with new
|
||||
* mm->pgd
|
||||
*/
|
||||
case 0:
|
||||
/* context created by exec, set asce limit to 4TB */
|
||||
mm->context.asce_bits = _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_REGION3;
|
||||
mm->context.asce_limit = STACK_TOP_MAX;
|
||||
} else if (mm->context.asce_limit == (1UL << 31)) {
|
||||
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_REGION3;
|
||||
break;
|
||||
case 1UL << 53:
|
||||
/* forked 4-level task, set new asce with new mm->pgd */
|
||||
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_REGION2;
|
||||
break;
|
||||
case 1UL << 31:
|
||||
/* forked 2-level compat task, set new asce with new mm->pgd */
|
||||
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_SEGMENT;
|
||||
/* pgd_alloc() did not increase mm->nr_pmds */
|
||||
mm_inc_nr_pmds(mm);
|
||||
}
|
||||
crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
|
||||
|
@ -42,7 +58,7 @@ static inline int init_new_context(struct task_struct *tsk,
|
|||
|
||||
static inline void set_user_asce(struct mm_struct *mm)
|
||||
{
|
||||
S390_lowcore.user_asce = mm->context.asce_bits | __pa(mm->pgd);
|
||||
S390_lowcore.user_asce = mm->context.asce;
|
||||
if (current->thread.mm_segment.ar4)
|
||||
__ctl_load(S390_lowcore.user_asce, 7, 7);
|
||||
set_cpu_flag(CIF_ASCE);
|
||||
|
@ -71,7 +87,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
|||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
S390_lowcore.user_asce = next->context.asce_bits | __pa(next->pgd);
|
||||
S390_lowcore.user_asce = next->context.asce;
|
||||
if (prev == next)
|
||||
return;
|
||||
if (MACHINE_HAS_TLB_LC)
|
||||
|
|
|
@ -44,7 +44,8 @@ struct zpci_fmb {
|
|||
u64 rpcit_ops;
|
||||
u64 dma_rbytes;
|
||||
u64 dma_wbytes;
|
||||
} __packed __aligned(64);
|
||||
u64 pad[2];
|
||||
} __packed __aligned(128);
|
||||
|
||||
enum zpci_state {
|
||||
ZPCI_FN_STATE_RESERVED,
|
||||
|
|
|
@ -52,8 +52,8 @@ static inline unsigned long pgd_entry_type(struct mm_struct *mm)
|
|||
return _REGION2_ENTRY_EMPTY;
|
||||
}
|
||||
|
||||
int crst_table_upgrade(struct mm_struct *, unsigned long limit);
|
||||
void crst_table_downgrade(struct mm_struct *, unsigned long limit);
|
||||
int crst_table_upgrade(struct mm_struct *);
|
||||
void crst_table_downgrade(struct mm_struct *);
|
||||
|
||||
static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address)
|
||||
{
|
||||
|
|
|
@ -175,7 +175,7 @@ extern __vector128 init_task_fpu_regs[__NUM_VXRS];
|
|||
regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
|
||||
regs->psw.addr = new_psw; \
|
||||
regs->gprs[15] = new_stackp; \
|
||||
crst_table_downgrade(current->mm, 1UL << 31); \
|
||||
crst_table_downgrade(current->mm); \
|
||||
execve_tail(); \
|
||||
} while (0)
|
||||
|
||||
|
|
|
@ -13,4 +13,6 @@
|
|||
#define __NR_seccomp_exit_32 __NR_exit
|
||||
#define __NR_seccomp_sigreturn_32 __NR_sigreturn
|
||||
|
||||
#include <asm-generic/seccomp.h>
|
||||
|
||||
#endif /* _ASM_S390_SECCOMP_H */
|
||||
|
|
|
@ -110,8 +110,7 @@ static inline void __tlb_flush_asce(struct mm_struct *mm, unsigned long asce)
|
|||
static inline void __tlb_flush_kernel(void)
|
||||
{
|
||||
if (MACHINE_HAS_IDTE)
|
||||
__tlb_flush_idte((unsigned long) init_mm.pgd |
|
||||
init_mm.context.asce_bits);
|
||||
__tlb_flush_idte(init_mm.context.asce);
|
||||
else
|
||||
__tlb_flush_global();
|
||||
}
|
||||
|
@ -133,8 +132,7 @@ static inline void __tlb_flush_asce(struct mm_struct *mm, unsigned long asce)
|
|||
static inline void __tlb_flush_kernel(void)
|
||||
{
|
||||
if (MACHINE_HAS_TLB_LC)
|
||||
__tlb_flush_idte_local((unsigned long) init_mm.pgd |
|
||||
init_mm.context.asce_bits);
|
||||
__tlb_flush_idte_local(init_mm.context.asce);
|
||||
else
|
||||
__tlb_flush_local();
|
||||
}
|
||||
|
@ -148,8 +146,7 @@ static inline void __tlb_flush_mm(struct mm_struct * mm)
|
|||
* only ran on the local cpu.
|
||||
*/
|
||||
if (MACHINE_HAS_IDTE && list_empty(&mm->context.gmap_list))
|
||||
__tlb_flush_asce(mm, (unsigned long) mm->pgd |
|
||||
mm->context.asce_bits);
|
||||
__tlb_flush_asce(mm, mm->context.asce);
|
||||
else
|
||||
__tlb_flush_full(mm);
|
||||
}
|
||||
|
|
|
@ -105,6 +105,7 @@ void arch_spin_lock_wait_flags(arch_spinlock_t *lp, unsigned long flags)
|
|||
if (_raw_compare_and_swap(&lp->lock, 0, cpu))
|
||||
return;
|
||||
local_irq_restore(flags);
|
||||
continue;
|
||||
}
|
||||
/* Check if the lock owner is running. */
|
||||
if (first_diag && cpu_is_preempted(~owner)) {
|
||||
|
|
|
@ -89,7 +89,8 @@ void __init paging_init(void)
|
|||
asce_bits = _ASCE_TYPE_REGION3 | _ASCE_TABLE_LENGTH;
|
||||
pgd_type = _REGION3_ENTRY_EMPTY;
|
||||
}
|
||||
S390_lowcore.kernel_asce = (__pa(init_mm.pgd) & PAGE_MASK) | asce_bits;
|
||||
init_mm.context.asce = (__pa(init_mm.pgd) & PAGE_MASK) | asce_bits;
|
||||
S390_lowcore.kernel_asce = init_mm.context.asce;
|
||||
clear_table((unsigned long *) init_mm.pgd, pgd_type,
|
||||
sizeof(unsigned long)*2048);
|
||||
vmem_map_init();
|
||||
|
|
|
@ -174,7 +174,7 @@ int s390_mmap_check(unsigned long addr, unsigned long len, unsigned long flags)
|
|||
if (!(flags & MAP_FIXED))
|
||||
addr = 0;
|
||||
if ((addr + len) >= TASK_SIZE)
|
||||
return crst_table_upgrade(current->mm, TASK_MAX_SIZE);
|
||||
return crst_table_upgrade(current->mm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -191,7 +191,7 @@ s390_get_unmapped_area(struct file *filp, unsigned long addr,
|
|||
return area;
|
||||
if (area == -ENOMEM && !is_compat_task() && TASK_SIZE < TASK_MAX_SIZE) {
|
||||
/* Upgrade the page table to 4 levels and retry. */
|
||||
rc = crst_table_upgrade(mm, TASK_MAX_SIZE);
|
||||
rc = crst_table_upgrade(mm);
|
||||
if (rc)
|
||||
return (unsigned long) rc;
|
||||
area = arch_get_unmapped_area(filp, addr, len, pgoff, flags);
|
||||
|
@ -213,7 +213,7 @@ s390_get_unmapped_area_topdown(struct file *filp, const unsigned long addr,
|
|||
return area;
|
||||
if (area == -ENOMEM && !is_compat_task() && TASK_SIZE < TASK_MAX_SIZE) {
|
||||
/* Upgrade the page table to 4 levels and retry. */
|
||||
rc = crst_table_upgrade(mm, TASK_MAX_SIZE);
|
||||
rc = crst_table_upgrade(mm);
|
||||
if (rc)
|
||||
return (unsigned long) rc;
|
||||
area = arch_get_unmapped_area_topdown(filp, addr, len,
|
||||
|
|
|
@ -76,81 +76,52 @@ static void __crst_table_upgrade(void *arg)
|
|||
__tlb_flush_local();
|
||||
}
|
||||
|
||||
int crst_table_upgrade(struct mm_struct *mm, unsigned long limit)
|
||||
int crst_table_upgrade(struct mm_struct *mm)
|
||||
{
|
||||
unsigned long *table, *pgd;
|
||||
unsigned long entry;
|
||||
int flush;
|
||||
|
||||
BUG_ON(limit > TASK_MAX_SIZE);
|
||||
flush = 0;
|
||||
repeat:
|
||||
/* upgrade should only happen from 3 to 4 levels */
|
||||
BUG_ON(mm->context.asce_limit != (1UL << 42));
|
||||
|
||||
table = crst_table_alloc(mm);
|
||||
if (!table)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_bh(&mm->page_table_lock);
|
||||
if (mm->context.asce_limit < limit) {
|
||||
pgd = (unsigned long *) mm->pgd;
|
||||
if (mm->context.asce_limit <= (1UL << 31)) {
|
||||
entry = _REGION3_ENTRY_EMPTY;
|
||||
mm->context.asce_limit = 1UL << 42;
|
||||
mm->context.asce_bits = _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS |
|
||||
_ASCE_TYPE_REGION3;
|
||||
} else {
|
||||
entry = _REGION2_ENTRY_EMPTY;
|
||||
mm->context.asce_limit = 1UL << 53;
|
||||
mm->context.asce_bits = _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS |
|
||||
_ASCE_TYPE_REGION2;
|
||||
}
|
||||
crst_table_init(table, entry);
|
||||
pgd_populate(mm, (pgd_t *) table, (pud_t *) pgd);
|
||||
mm->pgd = (pgd_t *) table;
|
||||
mm->task_size = mm->context.asce_limit;
|
||||
table = NULL;
|
||||
flush = 1;
|
||||
}
|
||||
pgd = (unsigned long *) mm->pgd;
|
||||
crst_table_init(table, _REGION2_ENTRY_EMPTY);
|
||||
pgd_populate(mm, (pgd_t *) table, (pud_t *) pgd);
|
||||
mm->pgd = (pgd_t *) table;
|
||||
mm->context.asce_limit = 1UL << 53;
|
||||
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_REGION2;
|
||||
mm->task_size = mm->context.asce_limit;
|
||||
spin_unlock_bh(&mm->page_table_lock);
|
||||
if (table)
|
||||
crst_table_free(mm, table);
|
||||
if (mm->context.asce_limit < limit)
|
||||
goto repeat;
|
||||
if (flush)
|
||||
on_each_cpu(__crst_table_upgrade, mm, 0);
|
||||
|
||||
on_each_cpu(__crst_table_upgrade, mm, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void crst_table_downgrade(struct mm_struct *mm, unsigned long limit)
|
||||
void crst_table_downgrade(struct mm_struct *mm)
|
||||
{
|
||||
pgd_t *pgd;
|
||||
|
||||
/* downgrade should only happen from 3 to 2 levels (compat only) */
|
||||
BUG_ON(mm->context.asce_limit != (1UL << 42));
|
||||
|
||||
if (current->active_mm == mm) {
|
||||
clear_user_asce();
|
||||
__tlb_flush_mm(mm);
|
||||
}
|
||||
while (mm->context.asce_limit > limit) {
|
||||
pgd = mm->pgd;
|
||||
switch (pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) {
|
||||
case _REGION_ENTRY_TYPE_R2:
|
||||
mm->context.asce_limit = 1UL << 42;
|
||||
mm->context.asce_bits = _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS |
|
||||
_ASCE_TYPE_REGION3;
|
||||
break;
|
||||
case _REGION_ENTRY_TYPE_R3:
|
||||
mm->context.asce_limit = 1UL << 31;
|
||||
mm->context.asce_bits = _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS |
|
||||
_ASCE_TYPE_SEGMENT;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
mm->pgd = (pgd_t *) (pgd_val(*pgd) & _REGION_ENTRY_ORIGIN);
|
||||
mm->task_size = mm->context.asce_limit;
|
||||
crst_table_free(mm, (unsigned long *) pgd);
|
||||
}
|
||||
|
||||
pgd = mm->pgd;
|
||||
mm->pgd = (pgd_t *) (pgd_val(*pgd) & _REGION_ENTRY_ORIGIN);
|
||||
mm->context.asce_limit = 1UL << 31;
|
||||
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | _ASCE_TYPE_SEGMENT;
|
||||
mm->task_size = mm->context.asce_limit;
|
||||
crst_table_free(mm, (unsigned long *) pgd);
|
||||
|
||||
if (current->active_mm == mm)
|
||||
set_user_asce(mm);
|
||||
}
|
||||
|
|
|
@ -457,7 +457,7 @@ int zpci_dma_init_device(struct zpci_dev *zdev)
|
|||
zdev->dma_table = dma_alloc_cpu_table();
|
||||
if (!zdev->dma_table) {
|
||||
rc = -ENOMEM;
|
||||
goto out_clean;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -477,18 +477,22 @@ int zpci_dma_init_device(struct zpci_dev *zdev)
|
|||
zdev->iommu_bitmap = vzalloc(zdev->iommu_pages / 8);
|
||||
if (!zdev->iommu_bitmap) {
|
||||
rc = -ENOMEM;
|
||||
goto out_reg;
|
||||
goto free_dma_table;
|
||||
}
|
||||
|
||||
rc = zpci_register_ioat(zdev, 0, zdev->start_dma, zdev->end_dma,
|
||||
(u64) zdev->dma_table);
|
||||
if (rc)
|
||||
goto out_reg;
|
||||
return 0;
|
||||
goto free_bitmap;
|
||||
|
||||
out_reg:
|
||||
return 0;
|
||||
free_bitmap:
|
||||
vfree(zdev->iommu_bitmap);
|
||||
zdev->iommu_bitmap = NULL;
|
||||
free_dma_table:
|
||||
dma_free_cpu_table(zdev->dma_table);
|
||||
out_clean:
|
||||
zdev->dma_table = NULL;
|
||||
out:
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
|
|
@ -453,10 +453,10 @@ static int sha_complete_job(struct mcryptd_hash_request_ctx *rctx,
|
|||
|
||||
req = cast_mcryptd_ctx_to_req(req_ctx);
|
||||
if (irqs_disabled())
|
||||
rctx->complete(&req->base, ret);
|
||||
req_ctx->complete(&req->base, ret);
|
||||
else {
|
||||
local_bh_disable();
|
||||
rctx->complete(&req->base, ret);
|
||||
req_ctx->complete(&req->base, ret);
|
||||
local_bh_enable();
|
||||
}
|
||||
}
|
||||
|
|
|
@ -474,6 +474,7 @@ static __init int _init_perf_amd_iommu(
|
|||
|
||||
static struct perf_amd_iommu __perf_iommu = {
|
||||
.pmu = {
|
||||
.task_ctx_nr = perf_invalid_context,
|
||||
.event_init = perf_iommu_event_init,
|
||||
.add = perf_iommu_add,
|
||||
.del = perf_iommu_del,
|
||||
|
|
|
@ -3794,6 +3794,8 @@ __init int intel_pmu_init(void)
|
|||
pr_cont("Knights Landing events, ");
|
||||
break;
|
||||
|
||||
case 142: /* 14nm Kabylake Mobile */
|
||||
case 158: /* 14nm Kabylake Desktop */
|
||||
case 78: /* 14nm Skylake Mobile */
|
||||
case 94: /* 14nm Skylake Desktop */
|
||||
case 85: /* 14nm Skylake Server */
|
||||
|
|
|
@ -4,6 +4,7 @@
|
|||
#include <asm/page.h>
|
||||
#include <asm-generic/hugetlb.h>
|
||||
|
||||
#define hugepages_supported() cpu_has_pse
|
||||
|
||||
static inline int is_hugepage_only_range(struct mm_struct *mm,
|
||||
unsigned long addr,
|
||||
|
|
|
@ -256,7 +256,8 @@ static void clear_irq_vector(int irq, struct apic_chip_data *data)
|
|||
struct irq_desc *desc;
|
||||
int cpu, vector;
|
||||
|
||||
BUG_ON(!data->cfg.vector);
|
||||
if (!data->cfg.vector)
|
||||
return;
|
||||
|
||||
vector = data->cfg.vector;
|
||||
for_each_cpu_and(cpu, data->domain, cpu_online_mask)
|
||||
|
|
|
@ -152,6 +152,11 @@ static struct clocksource hyperv_cs = {
|
|||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static unsigned char hv_get_nmi_reason(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init ms_hyperv_init_platform(void)
|
||||
{
|
||||
/*
|
||||
|
@ -191,6 +196,13 @@ static void __init ms_hyperv_init_platform(void)
|
|||
machine_ops.crash_shutdown = hv_machine_crash_shutdown;
|
||||
#endif
|
||||
mark_tsc_unstable("running on Hyper-V");
|
||||
|
||||
/*
|
||||
* Generation 2 instances don't support reading the NMI status from
|
||||
* 0x61 port.
|
||||
*/
|
||||
if (efi_enabled(EFI_BOOT))
|
||||
x86_platform.get_nmi_reason = hv_get_nmi_reason;
|
||||
}
|
||||
|
||||
const __refconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
|
||||
|
|
|
@ -389,12 +389,6 @@ default_entry:
|
|||
/* Make changes effective */
|
||||
wrmsr
|
||||
|
||||
/*
|
||||
* And make sure that all the mappings we set up have NX set from
|
||||
* the beginning.
|
||||
*/
|
||||
orl $(1 << (_PAGE_BIT_NX - 32)), pa(__supported_pte_mask + 4)
|
||||
|
||||
enable_paging:
|
||||
|
||||
/*
|
||||
|
|
|
@ -32,8 +32,9 @@ early_param("noexec", noexec_setup);
|
|||
|
||||
void x86_configure_nx(void)
|
||||
{
|
||||
/* If disable_nx is set, clear NX on all new mappings going forward. */
|
||||
if (disable_nx)
|
||||
if (boot_cpu_has(X86_FEATURE_NX) && !disable_nx)
|
||||
__supported_pte_mask |= _PAGE_NX;
|
||||
else
|
||||
__supported_pte_mask &= ~_PAGE_NX;
|
||||
}
|
||||
|
||||
|
|
|
@ -27,6 +27,12 @@ static bool xen_pvspin = true;
|
|||
|
||||
static void xen_qlock_kick(int cpu)
|
||||
{
|
||||
int irq = per_cpu(lock_kicker_irq, cpu);
|
||||
|
||||
/* Don't kick if the target's kicker interrupt is not initialized. */
|
||||
if (irq == -1)
|
||||
return;
|
||||
|
||||
xen_send_IPI_one(cpu, XEN_SPIN_UNLOCK_VECTOR);
|
||||
}
|
||||
|
||||
|
|
|
@ -387,16 +387,16 @@ static int pkcs1pad_decrypt(struct akcipher_request *req)
|
|||
req_ctx->child_req.src = req->src;
|
||||
req_ctx->child_req.src_len = req->src_len;
|
||||
req_ctx->child_req.dst = req_ctx->out_sg;
|
||||
req_ctx->child_req.dst_len = ctx->key_size - 1;
|
||||
req_ctx->child_req.dst_len = ctx->key_size ;
|
||||
|
||||
req_ctx->out_buf = kmalloc(ctx->key_size - 1,
|
||||
req_ctx->out_buf = kmalloc(ctx->key_size,
|
||||
(req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
|
||||
GFP_KERNEL : GFP_ATOMIC);
|
||||
if (!req_ctx->out_buf)
|
||||
return -ENOMEM;
|
||||
|
||||
pkcs1pad_sg_set_buf(req_ctx->out_sg, req_ctx->out_buf,
|
||||
ctx->key_size - 1, NULL);
|
||||
ctx->key_size, NULL);
|
||||
|
||||
akcipher_request_set_tfm(&req_ctx->child_req, ctx->child);
|
||||
akcipher_request_set_callback(&req_ctx->child_req, req->base.flags,
|
||||
|
@ -595,16 +595,16 @@ static int pkcs1pad_verify(struct akcipher_request *req)
|
|||
req_ctx->child_req.src = req->src;
|
||||
req_ctx->child_req.src_len = req->src_len;
|
||||
req_ctx->child_req.dst = req_ctx->out_sg;
|
||||
req_ctx->child_req.dst_len = ctx->key_size - 1;
|
||||
req_ctx->child_req.dst_len = ctx->key_size;
|
||||
|
||||
req_ctx->out_buf = kmalloc(ctx->key_size - 1,
|
||||
req_ctx->out_buf = kmalloc(ctx->key_size,
|
||||
(req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
|
||||
GFP_KERNEL : GFP_ATOMIC);
|
||||
if (!req_ctx->out_buf)
|
||||
return -ENOMEM;
|
||||
|
||||
pkcs1pad_sg_set_buf(req_ctx->out_sg, req_ctx->out_buf,
|
||||
ctx->key_size - 1, NULL);
|
||||
ctx->key_size, NULL);
|
||||
|
||||
akcipher_request_set_tfm(&req_ctx->child_req, ctx->child);
|
||||
akcipher_request_set_callback(&req_ctx->child_req, req->base.flags,
|
||||
|
|
|
@ -136,7 +136,6 @@ static bool bcma_is_core_needed_early(u16 core_id)
|
|||
return false;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF) && defined(CONFIG_OF_ADDRESS)
|
||||
static struct device_node *bcma_of_find_child_device(struct platform_device *parent,
|
||||
struct bcma_device *core)
|
||||
{
|
||||
|
@ -184,7 +183,7 @@ static unsigned int bcma_of_get_irq(struct platform_device *parent,
|
|||
struct of_phandle_args out_irq;
|
||||
int ret;
|
||||
|
||||
if (!parent || !parent->dev.of_node)
|
||||
if (!IS_ENABLED(CONFIG_OF_IRQ) || !parent || !parent->dev.of_node)
|
||||
return 0;
|
||||
|
||||
ret = bcma_of_irq_parse(parent, core, &out_irq, num);
|
||||
|
@ -202,23 +201,15 @@ static void bcma_of_fill_device(struct platform_device *parent,
|
|||
{
|
||||
struct device_node *node;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_OF_IRQ))
|
||||
return;
|
||||
|
||||
node = bcma_of_find_child_device(parent, core);
|
||||
if (node)
|
||||
core->dev.of_node = node;
|
||||
|
||||
core->irq = bcma_of_get_irq(parent, core, 0);
|
||||
}
|
||||
#else
|
||||
static void bcma_of_fill_device(struct platform_device *parent,
|
||||
struct bcma_device *core)
|
||||
{
|
||||
}
|
||||
static inline unsigned int bcma_of_get_irq(struct platform_device *parent,
|
||||
struct bcma_device *core, int num)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
unsigned int bcma_core_irq(struct bcma_device *core, int num)
|
||||
{
|
||||
|
|
|
@ -538,7 +538,6 @@ static int _rbd_dev_v2_snap_size(struct rbd_device *rbd_dev, u64 snap_id,
|
|||
u8 *order, u64 *snap_size);
|
||||
static int _rbd_dev_v2_snap_features(struct rbd_device *rbd_dev, u64 snap_id,
|
||||
u64 *snap_features);
|
||||
static u64 rbd_snap_id_by_name(struct rbd_device *rbd_dev, const char *name);
|
||||
|
||||
static int rbd_open(struct block_device *bdev, fmode_t mode)
|
||||
{
|
||||
|
@ -3127,9 +3126,6 @@ static void rbd_watch_cb(u64 ver, u64 notify_id, u8 opcode, void *data)
|
|||
struct rbd_device *rbd_dev = (struct rbd_device *)data;
|
||||
int ret;
|
||||
|
||||
if (!rbd_dev)
|
||||
return;
|
||||
|
||||
dout("%s: \"%s\" notify_id %llu opcode %u\n", __func__,
|
||||
rbd_dev->header_name, (unsigned long long)notify_id,
|
||||
(unsigned int)opcode);
|
||||
|
@ -3263,6 +3259,9 @@ static void rbd_dev_header_unwatch_sync(struct rbd_device *rbd_dev)
|
|||
|
||||
ceph_osdc_cancel_event(rbd_dev->watch_event);
|
||||
rbd_dev->watch_event = NULL;
|
||||
|
||||
dout("%s flushing notifies\n", __func__);
|
||||
ceph_osdc_flush_notifies(&rbd_dev->rbd_client->client->osdc);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -3642,21 +3641,14 @@ static void rbd_exists_validate(struct rbd_device *rbd_dev)
|
|||
static void rbd_dev_update_size(struct rbd_device *rbd_dev)
|
||||
{
|
||||
sector_t size;
|
||||
bool removing;
|
||||
|
||||
/*
|
||||
* Don't hold the lock while doing disk operations,
|
||||
* or lock ordering will conflict with the bdev mutex via:
|
||||
* rbd_add() -> blkdev_get() -> rbd_open()
|
||||
* If EXISTS is not set, rbd_dev->disk may be NULL, so don't
|
||||
* try to update its size. If REMOVING is set, updating size
|
||||
* is just useless work since the device can't be opened.
|
||||
*/
|
||||
spin_lock_irq(&rbd_dev->lock);
|
||||
removing = test_bit(RBD_DEV_FLAG_REMOVING, &rbd_dev->flags);
|
||||
spin_unlock_irq(&rbd_dev->lock);
|
||||
/*
|
||||
* If the device is being removed, rbd_dev->disk has
|
||||
* been destroyed, so don't try to update its size
|
||||
*/
|
||||
if (!removing) {
|
||||
if (test_bit(RBD_DEV_FLAG_EXISTS, &rbd_dev->flags) &&
|
||||
!test_bit(RBD_DEV_FLAG_REMOVING, &rbd_dev->flags)) {
|
||||
size = (sector_t)rbd_dev->mapping.size / SECTOR_SIZE;
|
||||
dout("setting size to %llu sectors", (unsigned long long)size);
|
||||
set_capacity(rbd_dev->disk, size);
|
||||
|
@ -4191,7 +4183,7 @@ static int _rbd_dev_v2_snap_features(struct rbd_device *rbd_dev, u64 snap_id,
|
|||
__le64 features;
|
||||
__le64 incompat;
|
||||
} __attribute__ ((packed)) features_buf = { 0 };
|
||||
u64 incompat;
|
||||
u64 unsup;
|
||||
int ret;
|
||||
|
||||
ret = rbd_obj_method_sync(rbd_dev, rbd_dev->header_name,
|
||||
|
@ -4204,9 +4196,12 @@ static int _rbd_dev_v2_snap_features(struct rbd_device *rbd_dev, u64 snap_id,
|
|||
if (ret < sizeof (features_buf))
|
||||
return -ERANGE;
|
||||
|
||||
incompat = le64_to_cpu(features_buf.incompat);
|
||||
if (incompat & ~RBD_FEATURES_SUPPORTED)
|
||||
unsup = le64_to_cpu(features_buf.incompat) & ~RBD_FEATURES_SUPPORTED;
|
||||
if (unsup) {
|
||||
rbd_warn(rbd_dev, "image uses unsupported features: 0x%llx",
|
||||
unsup);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
*snap_features = le64_to_cpu(features_buf.features);
|
||||
|
||||
|
@ -5187,6 +5182,10 @@ out_err:
|
|||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* rbd_dev->header_rwsem must be locked for write and will be unlocked
|
||||
* upon return.
|
||||
*/
|
||||
static int rbd_dev_device_setup(struct rbd_device *rbd_dev)
|
||||
{
|
||||
int ret;
|
||||
|
@ -5195,7 +5194,7 @@ static int rbd_dev_device_setup(struct rbd_device *rbd_dev)
|
|||
|
||||
ret = rbd_dev_id_get(rbd_dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto err_out_unlock;
|
||||
|
||||
BUILD_BUG_ON(DEV_NAME_LEN
|
||||
< sizeof (RBD_DRV_NAME) + MAX_INT_FORMAT_WIDTH);
|
||||
|
@ -5236,8 +5235,9 @@ static int rbd_dev_device_setup(struct rbd_device *rbd_dev)
|
|||
/* Everything's ready. Announce the disk to the world. */
|
||||
|
||||
set_bit(RBD_DEV_FLAG_EXISTS, &rbd_dev->flags);
|
||||
add_disk(rbd_dev->disk);
|
||||
up_write(&rbd_dev->header_rwsem);
|
||||
|
||||
add_disk(rbd_dev->disk);
|
||||
pr_info("%s: added with size 0x%llx\n", rbd_dev->disk->disk_name,
|
||||
(unsigned long long) rbd_dev->mapping.size);
|
||||
|
||||
|
@ -5252,6 +5252,8 @@ err_out_blkdev:
|
|||
unregister_blkdev(rbd_dev->major, rbd_dev->name);
|
||||
err_out_id:
|
||||
rbd_dev_id_put(rbd_dev);
|
||||
err_out_unlock:
|
||||
up_write(&rbd_dev->header_rwsem);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -5442,6 +5444,7 @@ static ssize_t do_rbd_add(struct bus_type *bus,
|
|||
spec = NULL; /* rbd_dev now owns this */
|
||||
rbd_opts = NULL; /* rbd_dev now owns this */
|
||||
|
||||
down_write(&rbd_dev->header_rwsem);
|
||||
rc = rbd_dev_image_probe(rbd_dev, 0);
|
||||
if (rc < 0)
|
||||
goto err_out_rbd_dev;
|
||||
|
@ -5471,6 +5474,7 @@ out:
|
|||
return rc;
|
||||
|
||||
err_out_rbd_dev:
|
||||
up_write(&rbd_dev->header_rwsem);
|
||||
rbd_dev_destroy(rbd_dev);
|
||||
err_out_client:
|
||||
rbd_put_client(rbdc);
|
||||
|
@ -5577,12 +5581,6 @@ static ssize_t do_rbd_remove(struct bus_type *bus,
|
|||
return ret;
|
||||
|
||||
rbd_dev_header_unwatch_sync(rbd_dev);
|
||||
/*
|
||||
* flush remaining watch callbacks - these must be complete
|
||||
* before the osd_client is shutdown
|
||||
*/
|
||||
dout("%s: flushing notifies", __func__);
|
||||
ceph_osdc_flush_notifies(&rbd_dev->rbd_client->client->osdc);
|
||||
|
||||
/*
|
||||
* Don't free anything from rbd_dev->disk until after all
|
||||
|
|
|
@ -42,7 +42,7 @@ static void __init tango_clocksource_init(struct device_node *np)
|
|||
|
||||
ret = clocksource_mmio_init(xtal_in_cnt, "tango-xtal", xtal_freq, 350,
|
||||
32, clocksource_mmio_readl_up);
|
||||
if (!ret) {
|
||||
if (ret) {
|
||||
pr_err("%s: registration failed\n", np->full_name);
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -1491,6 +1491,9 @@ static unsigned int cpufreq_update_current_freq(struct cpufreq_policy *policy)
|
|||
{
|
||||
unsigned int new_freq;
|
||||
|
||||
if (cpufreq_suspended)
|
||||
return 0;
|
||||
|
||||
new_freq = cpufreq_driver->get(policy->cpu);
|
||||
if (!new_freq)
|
||||
return 0;
|
||||
|
|
|
@ -193,12 +193,8 @@ unsigned int dbs_update(struct cpufreq_policy *policy)
|
|||
wall_time = cur_wall_time - j_cdbs->prev_cpu_wall;
|
||||
j_cdbs->prev_cpu_wall = cur_wall_time;
|
||||
|
||||
if (cur_idle_time <= j_cdbs->prev_cpu_idle) {
|
||||
idle_time = 0;
|
||||
} else {
|
||||
idle_time = cur_idle_time - j_cdbs->prev_cpu_idle;
|
||||
j_cdbs->prev_cpu_idle = cur_idle_time;
|
||||
}
|
||||
idle_time = cur_idle_time - j_cdbs->prev_cpu_idle;
|
||||
j_cdbs->prev_cpu_idle = cur_idle_time;
|
||||
|
||||
if (ignore_nice) {
|
||||
u64 cur_nice = kcpustat_cpu(j).cpustat[CPUTIME_NICE];
|
||||
|
|
|
@ -813,6 +813,11 @@ static int core_get_max_pstate(void)
|
|||
if (err)
|
||||
goto skip_tar;
|
||||
|
||||
/* For level 1 and 2, bits[23:16] contain the ratio */
|
||||
if (tdp_ctrl)
|
||||
tdp_ratio >>= 16;
|
||||
|
||||
tdp_ratio &= 0xff; /* ratios are only 8 bits long */
|
||||
if (tdp_ratio - 1 == tar) {
|
||||
max_pstate = tar;
|
||||
pr_debug("max_pstate=TAC %x\n", max_pstate);
|
||||
|
@ -1130,6 +1135,10 @@ static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
|
|||
sample_ratio = div_fp(int_tofp(pid_params.sample_rate_ns),
|
||||
int_tofp(duration_ns));
|
||||
core_busy = mul_fp(core_busy, sample_ratio);
|
||||
} else {
|
||||
sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
|
||||
if (sample_ratio < int_tofp(1))
|
||||
core_busy = 0;
|
||||
}
|
||||
|
||||
cpu->sample.busy_scaled = core_busy;
|
||||
|
|
|
@ -225,6 +225,9 @@ static int ccp_aes_cmac_export(struct ahash_request *req, void *out)
|
|||
struct ccp_aes_cmac_req_ctx *rctx = ahash_request_ctx(req);
|
||||
struct ccp_aes_cmac_exp_ctx state;
|
||||
|
||||
/* Don't let anything leak to 'out' */
|
||||
memset(&state, 0, sizeof(state));
|
||||
|
||||
state.null_msg = rctx->null_msg;
|
||||
memcpy(state.iv, rctx->iv, sizeof(state.iv));
|
||||
state.buf_count = rctx->buf_count;
|
||||
|
|
|
@ -212,6 +212,9 @@ static int ccp_sha_export(struct ahash_request *req, void *out)
|
|||
struct ccp_sha_req_ctx *rctx = ahash_request_ctx(req);
|
||||
struct ccp_sha_exp_ctx state;
|
||||
|
||||
/* Don't let anything leak to 'out' */
|
||||
memset(&state, 0, sizeof(state));
|
||||
|
||||
state.type = rctx->type;
|
||||
state.msg_bits = rctx->msg_bits;
|
||||
state.first = rctx->first;
|
||||
|
|
|
@ -63,6 +63,14 @@ static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
|
|||
ptr->eptr = upper_32_bits(dma_addr);
|
||||
}
|
||||
|
||||
static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
|
||||
struct talitos_ptr *src_ptr, bool is_sec1)
|
||||
{
|
||||
dst_ptr->ptr = src_ptr->ptr;
|
||||
if (!is_sec1)
|
||||
dst_ptr->eptr = src_ptr->eptr;
|
||||
}
|
||||
|
||||
static void to_talitos_ptr_len(struct talitos_ptr *ptr, unsigned int len,
|
||||
bool is_sec1)
|
||||
{
|
||||
|
@ -1083,21 +1091,20 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
|
|||
sg_count = dma_map_sg(dev, areq->src, edesc->src_nents ?: 1,
|
||||
(areq->src == areq->dst) ? DMA_BIDIRECTIONAL
|
||||
: DMA_TO_DEVICE);
|
||||
|
||||
/* hmac data */
|
||||
desc->ptr[1].len = cpu_to_be16(areq->assoclen);
|
||||
if (sg_count > 1 &&
|
||||
(ret = sg_to_link_tbl_offset(areq->src, sg_count, 0,
|
||||
areq->assoclen,
|
||||
&edesc->link_tbl[tbl_off])) > 1) {
|
||||
tbl_off += ret;
|
||||
|
||||
to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
|
||||
sizeof(struct talitos_ptr), 0);
|
||||
desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
|
||||
|
||||
dma_sync_single_for_device(dev, edesc->dma_link_tbl,
|
||||
edesc->dma_len, DMA_BIDIRECTIONAL);
|
||||
|
||||
tbl_off += ret;
|
||||
} else {
|
||||
to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->src), 0);
|
||||
desc->ptr[1].j_extent = 0;
|
||||
|
@ -1126,11 +1133,13 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
|
|||
if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
|
||||
sg_link_tbl_len += authsize;
|
||||
|
||||
if (sg_count > 1 &&
|
||||
(ret = sg_to_link_tbl_offset(areq->src, sg_count, areq->assoclen,
|
||||
sg_link_tbl_len,
|
||||
&edesc->link_tbl[tbl_off])) > 1) {
|
||||
tbl_off += ret;
|
||||
if (sg_count == 1) {
|
||||
to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src) +
|
||||
areq->assoclen, 0);
|
||||
} else if ((ret = sg_to_link_tbl_offset(areq->src, sg_count,
|
||||
areq->assoclen, sg_link_tbl_len,
|
||||
&edesc->link_tbl[tbl_off])) >
|
||||
1) {
|
||||
desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
|
||||
to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
|
||||
tbl_off *
|
||||
|
@ -1138,8 +1147,10 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
|
|||
dma_sync_single_for_device(dev, edesc->dma_link_tbl,
|
||||
edesc->dma_len,
|
||||
DMA_BIDIRECTIONAL);
|
||||
} else
|
||||
to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src), 0);
|
||||
tbl_off += ret;
|
||||
} else {
|
||||
copy_talitos_ptr(&desc->ptr[4], &edesc->link_tbl[tbl_off], 0);
|
||||
}
|
||||
|
||||
/* cipher out */
|
||||
desc->ptr[5].len = cpu_to_be16(cryptlen);
|
||||
|
@ -1151,11 +1162,13 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
|
|||
|
||||
edesc->icv_ool = false;
|
||||
|
||||
if (sg_count > 1 &&
|
||||
(sg_count = sg_to_link_tbl_offset(areq->dst, sg_count,
|
||||
if (sg_count == 1) {
|
||||
to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst) +
|
||||
areq->assoclen, 0);
|
||||
} else if ((sg_count =
|
||||
sg_to_link_tbl_offset(areq->dst, sg_count,
|
||||
areq->assoclen, cryptlen,
|
||||
&edesc->link_tbl[tbl_off])) >
|
||||
1) {
|
||||
&edesc->link_tbl[tbl_off])) > 1) {
|
||||
struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
|
||||
|
||||
to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
|
||||
|
@ -1178,8 +1191,9 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
|
|||
edesc->dma_len, DMA_BIDIRECTIONAL);
|
||||
|
||||
edesc->icv_ool = true;
|
||||
} else
|
||||
to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst), 0);
|
||||
} else {
|
||||
copy_talitos_ptr(&desc->ptr[5], &edesc->link_tbl[tbl_off], 0);
|
||||
}
|
||||
|
||||
/* iv out */
|
||||
map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
|
||||
|
@ -2629,21 +2643,11 @@ struct talitos_crypto_alg {
|
|||
struct talitos_alg_template algt;
|
||||
};
|
||||
|
||||
static int talitos_cra_init(struct crypto_tfm *tfm)
|
||||
static int talitos_init_common(struct talitos_ctx *ctx,
|
||||
struct talitos_crypto_alg *talitos_alg)
|
||||
{
|
||||
struct crypto_alg *alg = tfm->__crt_alg;
|
||||
struct talitos_crypto_alg *talitos_alg;
|
||||
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
|
||||
struct talitos_private *priv;
|
||||
|
||||
if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
|
||||
talitos_alg = container_of(__crypto_ahash_alg(alg),
|
||||
struct talitos_crypto_alg,
|
||||
algt.alg.hash);
|
||||
else
|
||||
talitos_alg = container_of(alg, struct talitos_crypto_alg,
|
||||
algt.alg.crypto);
|
||||
|
||||
/* update context with ptr to dev */
|
||||
ctx->dev = talitos_alg->dev;
|
||||
|
||||
|
@ -2661,10 +2665,33 @@ static int talitos_cra_init(struct crypto_tfm *tfm)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int talitos_cra_init(struct crypto_tfm *tfm)
|
||||
{
|
||||
struct crypto_alg *alg = tfm->__crt_alg;
|
||||
struct talitos_crypto_alg *talitos_alg;
|
||||
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
|
||||
|
||||
if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
|
||||
talitos_alg = container_of(__crypto_ahash_alg(alg),
|
||||
struct talitos_crypto_alg,
|
||||
algt.alg.hash);
|
||||
else
|
||||
talitos_alg = container_of(alg, struct talitos_crypto_alg,
|
||||
algt.alg.crypto);
|
||||
|
||||
return talitos_init_common(ctx, talitos_alg);
|
||||
}
|
||||
|
||||
static int talitos_cra_init_aead(struct crypto_aead *tfm)
|
||||
{
|
||||
talitos_cra_init(crypto_aead_tfm(tfm));
|
||||
return 0;
|
||||
struct aead_alg *alg = crypto_aead_alg(tfm);
|
||||
struct talitos_crypto_alg *talitos_alg;
|
||||
struct talitos_ctx *ctx = crypto_aead_ctx(tfm);
|
||||
|
||||
talitos_alg = container_of(alg, struct talitos_crypto_alg,
|
||||
algt.alg.aead);
|
||||
|
||||
return talitos_init_common(ctx, talitos_alg);
|
||||
}
|
||||
|
||||
static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
|
||||
|
|
|
@ -1866,7 +1866,7 @@ static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
|
|||
|
||||
i7_dev = get_i7core_dev(mce->socketid);
|
||||
if (!i7_dev)
|
||||
return NOTIFY_BAD;
|
||||
return NOTIFY_DONE;
|
||||
|
||||
mci = i7_dev->mci;
|
||||
pvt = mci->pvt_info;
|
||||
|
|
|
@ -362,6 +362,7 @@ struct sbridge_pvt {
|
|||
|
||||
/* Memory type detection */
|
||||
bool is_mirrored, is_lockstep, is_close_pg;
|
||||
bool is_chan_hash;
|
||||
|
||||
/* Fifo double buffers */
|
||||
struct mce mce_entry[MCE_LOG_LEN];
|
||||
|
@ -1060,6 +1061,20 @@ static inline u8 sad_pkg_ha(u8 pkg)
|
|||
return (pkg >> 2) & 0x1;
|
||||
}
|
||||
|
||||
static int haswell_chan_hash(int idx, u64 addr)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* XOR even bits from 12:26 to bit0 of idx,
|
||||
* odd bits from 13:27 to bit1
|
||||
*/
|
||||
for (i = 12; i < 28; i += 2)
|
||||
idx ^= (addr >> i) & 3;
|
||||
|
||||
return idx;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
Memory check routines
|
||||
****************************************************************************/
|
||||
|
@ -1616,6 +1631,10 @@ static int get_dimm_config(struct mem_ctl_info *mci)
|
|||
KNL_MAX_CHANNELS : NUM_CHANNELS;
|
||||
u64 knl_mc_sizes[KNL_MAX_CHANNELS];
|
||||
|
||||
if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
|
||||
pci_read_config_dword(pvt->pci_ha0, HASWELL_HASYSDEFEATURE2, ®);
|
||||
pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
|
||||
}
|
||||
if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
|
||||
pvt->info.type == KNIGHTS_LANDING)
|
||||
pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
|
||||
|
@ -2118,12 +2137,15 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
|
|||
}
|
||||
|
||||
ch_way = TAD_CH(reg) + 1;
|
||||
sck_way = 1 << TAD_SOCK(reg);
|
||||
sck_way = TAD_SOCK(reg);
|
||||
|
||||
if (ch_way == 3)
|
||||
idx = addr >> 6;
|
||||
else
|
||||
else {
|
||||
idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
|
||||
if (pvt->is_chan_hash)
|
||||
idx = haswell_chan_hash(idx, addr);
|
||||
}
|
||||
idx = idx % ch_way;
|
||||
|
||||
/*
|
||||
|
@ -2157,7 +2179,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
|
|||
switch(ch_way) {
|
||||
case 2:
|
||||
case 4:
|
||||
sck_xch = 1 << sck_way * (ch_way >> 1);
|
||||
sck_xch = (1 << sck_way) * (ch_way >> 1);
|
||||
break;
|
||||
default:
|
||||
sprintf(msg, "Invalid mirror set. Can't decode addr");
|
||||
|
@ -2193,7 +2215,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
|
|||
|
||||
ch_addr = addr - offset;
|
||||
ch_addr >>= (6 + shiftup);
|
||||
ch_addr /= ch_way * sck_way;
|
||||
ch_addr /= sck_xch;
|
||||
ch_addr <<= (6 + shiftup);
|
||||
ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
|
||||
|
||||
|
@ -3146,7 +3168,7 @@ static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
|
|||
|
||||
mci = get_mci_for_node_id(mce->socketid);
|
||||
if (!mci)
|
||||
return NOTIFY_BAD;
|
||||
return NOTIFY_DONE;
|
||||
pvt = mci->pvt_info;
|
||||
|
||||
/*
|
||||
|
|
|
@ -202,29 +202,44 @@ static const struct variable_validate variable_validate[] = {
|
|||
{ NULL_GUID, "", NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* Check if @var_name matches the pattern given in @match_name.
|
||||
*
|
||||
* @var_name: an array of @len non-NUL characters.
|
||||
* @match_name: a NUL-terminated pattern string, optionally ending in "*". A
|
||||
* final "*" character matches any trailing characters @var_name,
|
||||
* including the case when there are none left in @var_name.
|
||||
* @match: on output, the number of non-wildcard characters in @match_name
|
||||
* that @var_name matches, regardless of the return value.
|
||||
* @return: whether @var_name fully matches @match_name.
|
||||
*/
|
||||
static bool
|
||||
variable_matches(const char *var_name, size_t len, const char *match_name,
|
||||
int *match)
|
||||
{
|
||||
for (*match = 0; ; (*match)++) {
|
||||
char c = match_name[*match];
|
||||
char u = var_name[*match];
|
||||
|
||||
/* Wildcard in the matching name means we've matched */
|
||||
if (c == '*')
|
||||
switch (c) {
|
||||
case '*':
|
||||
/* Wildcard in @match_name means we've matched. */
|
||||
return true;
|
||||
|
||||
/* Case sensitive match */
|
||||
if (!c && *match == len)
|
||||
return true;
|
||||
case '\0':
|
||||
/* @match_name has ended. Has @var_name too? */
|
||||
return (*match == len);
|
||||
|
||||
if (c != u)
|
||||
default:
|
||||
/*
|
||||
* We've reached a non-wildcard char in @match_name.
|
||||
* Continue only if there's an identical character in
|
||||
* @var_name.
|
||||
*/
|
||||
if (*match < len && c == var_name[*match])
|
||||
continue;
|
||||
return false;
|
||||
|
||||
if (!c)
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
|
|
|
@ -360,7 +360,7 @@ static struct cpuidle_ops psci_cpuidle_ops __initdata = {
|
|||
.init = psci_dt_cpu_init_idle,
|
||||
};
|
||||
|
||||
CPUIDLE_METHOD_OF_DECLARE(psci, "arm,psci", &psci_cpuidle_ops);
|
||||
CPUIDLE_METHOD_OF_DECLARE(psci, "psci", &psci_cpuidle_ops);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
|
@ -1591,6 +1591,7 @@ struct amdgpu_uvd {
|
|||
struct amdgpu_bo *vcpu_bo;
|
||||
void *cpu_addr;
|
||||
uint64_t gpu_addr;
|
||||
unsigned fw_version;
|
||||
void *saved_bo;
|
||||
atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
|
||||
struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
|
||||
|
|
|
@ -425,6 +425,10 @@ static int acp_resume(void *handle)
|
|||
struct acp_pm_domain *apd;
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
/* return early if no ACP */
|
||||
if (!adev->acp.acp_genpd)
|
||||
return 0;
|
||||
|
||||
/* SMU block will power on ACP irrespective of ACP runtime status.
|
||||
* Power off explicitly based on genpd ACP runtime status so that ACP
|
||||
* hw and ACP-genpd status are in sync.
|
||||
|
|
|
@ -63,10 +63,6 @@ bool amdgpu_has_atpx(void) {
|
|||
return amdgpu_atpx_priv.atpx_detected;
|
||||
}
|
||||
|
||||
bool amdgpu_has_atpx_dgpu_power_cntl(void) {
|
||||
return amdgpu_atpx_priv.atpx.functions.power_cntl;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_atpx_call - call an ATPX method
|
||||
*
|
||||
|
@ -146,6 +142,13 @@ static void amdgpu_atpx_parse_functions(struct amdgpu_atpx_functions *f, u32 mas
|
|||
*/
|
||||
static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
|
||||
{
|
||||
/* make sure required functions are enabled */
|
||||
/* dGPU power control is required */
|
||||
if (atpx->functions.power_cntl == false) {
|
||||
printk("ATPX dGPU power cntl not present, forcing\n");
|
||||
atpx->functions.power_cntl = true;
|
||||
}
|
||||
|
||||
if (atpx->functions.px_params) {
|
||||
union acpi_object *info;
|
||||
struct atpx_px_params output;
|
||||
|
|
|
@ -62,12 +62,6 @@ static const char *amdgpu_asic_name[] = {
|
|||
"LAST",
|
||||
};
|
||||
|
||||
#if defined(CONFIG_VGA_SWITCHEROO)
|
||||
bool amdgpu_has_atpx_dgpu_power_cntl(void);
|
||||
#else
|
||||
static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
|
||||
#endif
|
||||
|
||||
bool amdgpu_device_is_px(struct drm_device *dev)
|
||||
{
|
||||
struct amdgpu_device *adev = dev->dev_private;
|
||||
|
@ -1485,7 +1479,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
|
|||
|
||||
if (amdgpu_runtime_pm == 1)
|
||||
runtime = true;
|
||||
if (amdgpu_device_is_px(ddev) && amdgpu_has_atpx_dgpu_power_cntl())
|
||||
if (amdgpu_device_is_px(ddev))
|
||||
runtime = true;
|
||||
vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
|
||||
if (runtime)
|
||||
|
|
|
@ -303,7 +303,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
|
|||
fw_info.feature = adev->vce.fb_version;
|
||||
break;
|
||||
case AMDGPU_INFO_FW_UVD:
|
||||
fw_info.ver = 0;
|
||||
fw_info.ver = adev->uvd.fw_version;
|
||||
fw_info.feature = 0;
|
||||
break;
|
||||
case AMDGPU_INFO_FW_GMC:
|
||||
|
|
|
@ -53,7 +53,7 @@ struct amdgpu_hpd;
|
|||
|
||||
#define AMDGPU_MAX_HPD_PINS 6
|
||||
#define AMDGPU_MAX_CRTCS 6
|
||||
#define AMDGPU_MAX_AFMT_BLOCKS 7
|
||||
#define AMDGPU_MAX_AFMT_BLOCKS 9
|
||||
|
||||
enum amdgpu_rmx_type {
|
||||
RMX_OFF,
|
||||
|
@ -309,8 +309,8 @@ struct amdgpu_mode_info {
|
|||
struct atom_context *atom_context;
|
||||
struct card_info *atom_card_info;
|
||||
bool mode_config_initialized;
|
||||
struct amdgpu_crtc *crtcs[6];
|
||||
struct amdgpu_afmt *afmt[7];
|
||||
struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
|
||||
struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
|
||||
/* DVI-I properties */
|
||||
struct drm_property *coherent_mode_property;
|
||||
/* DAC enable load detect */
|
||||
|
|
|
@ -223,6 +223,8 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
|
|||
{
|
||||
struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
|
||||
|
||||
if (amdgpu_ttm_tt_get_usermm(bo->ttm))
|
||||
return -EPERM;
|
||||
return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
|
||||
}
|
||||
|
||||
|
|
|
@ -158,6 +158,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
|
|||
DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
|
||||
version_major, version_minor, family_id);
|
||||
|
||||
adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
|
||||
(family_id << 8));
|
||||
|
||||
bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
|
||||
+ AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
|
||||
r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
|
||||
|
@ -255,6 +258,8 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
|
|||
if (i == AMDGPU_MAX_UVD_HANDLES)
|
||||
return 0;
|
||||
|
||||
cancel_delayed_work_sync(&adev->uvd.idle_work);
|
||||
|
||||
size = amdgpu_bo_size(adev->uvd.vcpu_bo);
|
||||
ptr = adev->uvd.cpu_addr;
|
||||
|
||||
|
|
|
@ -234,6 +234,7 @@ int amdgpu_vce_suspend(struct amdgpu_device *adev)
|
|||
if (i == AMDGPU_MAX_VCE_HANDLES)
|
||||
return 0;
|
||||
|
||||
cancel_delayed_work_sync(&adev->vce.idle_work);
|
||||
/* TODO: suspending running encoding sessions isn't supported */
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
@ -910,7 +910,10 @@ static int gmc_v7_0_late_init(void *handle)
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
|
||||
if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
|
||||
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gmc_v7_0_sw_init(void *handle)
|
||||
|
|
|
@ -870,7 +870,10 @@ static int gmc_v8_0_late_init(void *handle)
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
|
||||
if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
|
||||
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define mmMC_SEQ_MISC0_FIJI 0xA71
|
||||
|
|
|
@ -1672,13 +1672,19 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr,
|
|||
u8 sinks[DRM_DP_MAX_SDP_STREAMS];
|
||||
int i;
|
||||
|
||||
port = drm_dp_get_validated_port_ref(mgr, port);
|
||||
if (!port)
|
||||
return -EINVAL;
|
||||
|
||||
port_num = port->port_num;
|
||||
mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent);
|
||||
if (!mstb) {
|
||||
mstb = drm_dp_get_last_connected_port_and_mstb(mgr, port->parent, &port_num);
|
||||
|
||||
if (!mstb)
|
||||
if (!mstb) {
|
||||
drm_dp_put_port(port);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
|
||||
|
@ -1707,6 +1713,7 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr,
|
|||
kfree(txmsg);
|
||||
fail_put:
|
||||
drm_dp_put_mst_branch_device(mstb);
|
||||
drm_dp_put_port(port);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -1789,6 +1796,11 @@ int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr)
|
|||
req_payload.start_slot = cur_slots;
|
||||
if (mgr->proposed_vcpis[i]) {
|
||||
port = container_of(mgr->proposed_vcpis[i], struct drm_dp_mst_port, vcpi);
|
||||
port = drm_dp_get_validated_port_ref(mgr, port);
|
||||
if (!port) {
|
||||
mutex_unlock(&mgr->payload_lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
req_payload.num_slots = mgr->proposed_vcpis[i]->num_slots;
|
||||
req_payload.vcpi = mgr->proposed_vcpis[i]->vcpi;
|
||||
} else {
|
||||
|
@ -1816,6 +1828,9 @@ int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr)
|
|||
mgr->payloads[i].payload_state = req_payload.payload_state;
|
||||
}
|
||||
cur_slots += req_payload.num_slots;
|
||||
|
||||
if (port)
|
||||
drm_dp_put_port(port);
|
||||
}
|
||||
|
||||
for (i = 0; i < mgr->max_payloads; i++) {
|
||||
|
@ -2121,6 +2136,8 @@ int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr)
|
|||
|
||||
if (mgr->mst_primary) {
|
||||
int sret;
|
||||
u8 guid[16];
|
||||
|
||||
sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
|
||||
if (sret != DP_RECEIVER_CAP_SIZE) {
|
||||
DRM_DEBUG_KMS("dpcd read failed - undocked during suspend?\n");
|
||||
|
@ -2135,6 +2152,16 @@ int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr)
|
|||
ret = -1;
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
/* Some hubs forget their guids after they resume */
|
||||
sret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
|
||||
if (sret != 16) {
|
||||
DRM_DEBUG_KMS("dpcd read failed - undocked during suspend?\n");
|
||||
ret = -1;
|
||||
goto out_unlock;
|
||||
}
|
||||
drm_dp_check_mstb_guid(mgr->mst_primary, guid);
|
||||
|
||||
ret = 0;
|
||||
} else
|
||||
ret = -1;
|
||||
|
|
|
@ -572,6 +572,24 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
|
|||
goto fail;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the GPU linear window to be at the end of the DMA window, where
|
||||
* the CMA area is likely to reside. This ensures that we are able to
|
||||
* map the command buffers while having the linear window overlap as
|
||||
* much RAM as possible, so we can optimize mappings for other buffers.
|
||||
*
|
||||
* For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
|
||||
* to different views of the memory on the individual engines.
|
||||
*/
|
||||
if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
|
||||
(gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
|
||||
u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
|
||||
if (dma_mask < PHYS_OFFSET + SZ_2G)
|
||||
gpu->memory_base = PHYS_OFFSET;
|
||||
else
|
||||
gpu->memory_base = dma_mask - SZ_2G + 1;
|
||||
}
|
||||
|
||||
ret = etnaviv_hw_reset(gpu);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
@ -1566,7 +1584,6 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct etnaviv_gpu *gpu;
|
||||
u32 dma_mask;
|
||||
int err = 0;
|
||||
|
||||
gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
|
||||
|
@ -1576,18 +1593,6 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
|
|||
gpu->dev = &pdev->dev;
|
||||
mutex_init(&gpu->lock);
|
||||
|
||||
/*
|
||||
* Set the GPU linear window to be at the end of the DMA window, where
|
||||
* the CMA area is likely to reside. This ensures that we are able to
|
||||
* map the command buffers while having the linear window overlap as
|
||||
* much RAM as possible, so we can optimize mappings for other buffers.
|
||||
*/
|
||||
dma_mask = (u32)dma_get_required_mask(dev);
|
||||
if (dma_mask < PHYS_OFFSET + SZ_2G)
|
||||
gpu->memory_base = PHYS_OFFSET;
|
||||
else
|
||||
gpu->memory_base = dma_mask - SZ_2G + 1;
|
||||
|
||||
/* Map registers: */
|
||||
gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
|
||||
if (IS_ERR(gpu->mmio))
|
||||
|
|
|
@ -2634,8 +2634,9 @@ struct drm_i915_cmd_table {
|
|||
|
||||
/* WaRsDisableCoarsePowerGating:skl,bxt */
|
||||
#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
|
||||
((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
|
||||
IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
|
||||
IS_SKL_GT3(dev) || \
|
||||
IS_SKL_GT4(dev))
|
||||
|
||||
/*
|
||||
* dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
|
||||
* even when in MSI mode. This results in spurious interrupt warnings if the
|
||||
|
|
|
@ -501,19 +501,24 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work)
|
|||
if (pvec != NULL) {
|
||||
struct mm_struct *mm = obj->userptr.mm->mm;
|
||||
|
||||
down_read(&mm->mmap_sem);
|
||||
while (pinned < npages) {
|
||||
ret = get_user_pages_remote(work->task, mm,
|
||||
obj->userptr.ptr + pinned * PAGE_SIZE,
|
||||
npages - pinned,
|
||||
!obj->userptr.read_only, 0,
|
||||
pvec + pinned, NULL);
|
||||
if (ret < 0)
|
||||
break;
|
||||
ret = -EFAULT;
|
||||
if (atomic_inc_not_zero(&mm->mm_users)) {
|
||||
down_read(&mm->mmap_sem);
|
||||
while (pinned < npages) {
|
||||
ret = get_user_pages_remote
|
||||
(work->task, mm,
|
||||
obj->userptr.ptr + pinned * PAGE_SIZE,
|
||||
npages - pinned,
|
||||
!obj->userptr.read_only, 0,
|
||||
pvec + pinned, NULL);
|
||||
if (ret < 0)
|
||||
break;
|
||||
|
||||
pinned += ret;
|
||||
pinned += ret;
|
||||
}
|
||||
up_read(&mm->mmap_sem);
|
||||
mmput(mm);
|
||||
}
|
||||
up_read(&mm->mmap_sem);
|
||||
}
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
|
|
|
@ -841,11 +841,11 @@ static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
|
|||
if (unlikely(total_bytes > remain_usable)) {
|
||||
/*
|
||||
* The base request will fit but the reserved space
|
||||
* falls off the end. So only need to to wait for the
|
||||
* reserved size after flushing out the remainder.
|
||||
* falls off the end. So don't need an immediate wrap
|
||||
* and only need to effectively wait for the reserved
|
||||
* size space from the start of ringbuffer.
|
||||
*/
|
||||
wait_bytes = remain_actual + ringbuf->reserved_size;
|
||||
need_wrap = true;
|
||||
} else if (total_bytes > ringbuf->space) {
|
||||
/* No wrapping required, just waiting. */
|
||||
wait_bytes = total_bytes;
|
||||
|
@ -1913,15 +1913,18 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
|
|||
struct intel_ringbuffer *ringbuf = request->ringbuf;
|
||||
int ret;
|
||||
|
||||
ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
|
||||
ret = intel_logical_ring_begin(request, 8 + WA_TAIL_DWORDS);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* We're using qword write, seqno should be aligned to 8 bytes. */
|
||||
BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
|
||||
|
||||
/* w/a for post sync ops following a GPGPU operation we
|
||||
* need a prior CS_STALL, which is emitted by the flush
|
||||
* following the batch.
|
||||
*/
|
||||
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
|
||||
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
|
||||
intel_logical_ring_emit(ringbuf,
|
||||
(PIPE_CONTROL_GLOBAL_GTT_IVB |
|
||||
PIPE_CONTROL_CS_STALL |
|
||||
|
@ -1929,7 +1932,10 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
|
|||
intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));
|
||||
intel_logical_ring_emit(ringbuf, 0);
|
||||
intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
|
||||
/* We're thrashing one dword of HWS. */
|
||||
intel_logical_ring_emit(ringbuf, 0);
|
||||
intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
|
||||
intel_logical_ring_emit(ringbuf, MI_NOOP);
|
||||
return intel_logical_ring_advance_and_submit(request);
|
||||
}
|
||||
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue