firmware: qcom_scm-64: Add atomic version of qcom_scm_call
There are scnenarios where drivers are required to make a scm call in atomic context, such as in one of the qcom's arm-smmu-500 errata [1]. [1] ("https://source.codeaurora.org/quic/la/kernel/msm-4.9/ tree/drivers/iommu/arm-smmu.c?h=msm-4.9#n4842") Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Andy Gross <agross@kernel.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Will Deacon <will@kernel.org>
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@ -62,32 +62,72 @@ static DEFINE_MUTEX(qcom_scm_lock);
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#define FIRST_EXT_ARG_IDX 3
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#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
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/**
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* qcom_scm_call() - Invoke a syscall in the secure world
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* @dev: device
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @desc: Descriptor structure containing arguments and return values
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*
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* Sends a command to the SCM and waits for the command to finish processing.
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* This should *only* be called in pre-emptible context.
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*/
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static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
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const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res)
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static void __qcom_scm_call_do(const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res, u32 fn_id,
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u64 x5, u32 type)
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{
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u64 cmd;
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struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 };
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cmd = ARM_SMCCC_CALL_VAL(type, qcom_smccc_convention,
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ARM_SMCCC_OWNER_SIP, fn_id);
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quirk.state.a6 = 0;
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do {
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arm_smccc_smc_quirk(cmd, desc->arginfo, desc->args[0],
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desc->args[1], desc->args[2], x5,
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quirk.state.a6, 0, res, &quirk);
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if (res->a0 == QCOM_SCM_INTERRUPTED)
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cmd = res->a0;
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} while (res->a0 == QCOM_SCM_INTERRUPTED);
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}
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static void qcom_scm_call_do(const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res, u32 fn_id,
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u64 x5, bool atomic)
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{
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int retry_count = 0;
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if (atomic) {
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__qcom_scm_call_do(desc, res, fn_id, x5, ARM_SMCCC_FAST_CALL);
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return;
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}
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do {
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mutex_lock(&qcom_scm_lock);
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__qcom_scm_call_do(desc, res, fn_id, x5,
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ARM_SMCCC_STD_CALL);
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mutex_unlock(&qcom_scm_lock);
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if (res->a0 == QCOM_SCM_V2_EBUSY) {
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if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
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break;
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msleep(QCOM_SCM_EBUSY_WAIT_MS);
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}
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} while (res->a0 == QCOM_SCM_V2_EBUSY);
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}
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static int ___qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
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const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res, bool atomic)
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{
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int arglen = desc->arginfo & 0xf;
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int retry_count = 0, i;
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int i;
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u32 fn_id = QCOM_SCM_FNID(svc_id, cmd_id);
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u64 cmd, x5 = desc->args[FIRST_EXT_ARG_IDX];
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u64 x5 = desc->args[FIRST_EXT_ARG_IDX];
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dma_addr_t args_phys = 0;
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void *args_virt = NULL;
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size_t alloc_len;
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struct arm_smccc_quirk quirk = {.id = ARM_SMCCC_QUIRK_QCOM_A6};
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gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
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if (unlikely(arglen > N_REGISTER_ARGS)) {
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alloc_len = N_EXT_QCOM_SCM_ARGS * sizeof(u64);
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args_virt = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
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args_virt = kzalloc(PAGE_ALIGN(alloc_len), flag);
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if (!args_virt)
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return -ENOMEM;
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@ -117,33 +157,7 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
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x5 = args_phys;
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}
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do {
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mutex_lock(&qcom_scm_lock);
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cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL,
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qcom_smccc_convention,
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ARM_SMCCC_OWNER_SIP, fn_id);
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quirk.state.a6 = 0;
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do {
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arm_smccc_smc_quirk(cmd, desc->arginfo, desc->args[0],
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desc->args[1], desc->args[2], x5,
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quirk.state.a6, 0, res, &quirk);
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if (res->a0 == QCOM_SCM_INTERRUPTED)
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cmd = res->a0;
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} while (res->a0 == QCOM_SCM_INTERRUPTED);
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mutex_unlock(&qcom_scm_lock);
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if (res->a0 == QCOM_SCM_V2_EBUSY) {
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if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
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break;
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msleep(QCOM_SCM_EBUSY_WAIT_MS);
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}
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} while (res->a0 == QCOM_SCM_V2_EBUSY);
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qcom_scm_call_do(desc, res, fn_id, x5, atomic);
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if (args_virt) {
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dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
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@ -156,6 +170,42 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
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return 0;
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}
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/**
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* qcom_scm_call() - Invoke a syscall in the secure world
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* @dev: device
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @desc: Descriptor structure containing arguments and return values
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*
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* Sends a command to the SCM and waits for the command to finish processing.
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* This should *only* be called in pre-emptible context.
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*/
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static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
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const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res)
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{
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might_sleep();
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return ___qcom_scm_call(dev, svc_id, cmd_id, desc, res, false);
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}
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/**
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* qcom_scm_call_atomic() - atomic variation of qcom_scm_call()
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* @dev: device
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @desc: Descriptor structure containing arguments and return values
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* @res: Structure containing results from SMC/HVC call
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*
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* Sends a command to the SCM and waits for the command to finish processing.
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* This can be called in atomic context.
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*/
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static int qcom_scm_call_atomic(struct device *dev, u32 svc_id, u32 cmd_id,
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const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res)
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{
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return ___qcom_scm_call(dev, svc_id, cmd_id, desc, res, true);
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}
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/**
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* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
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* @entry: Entry point function for the cpus
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