UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

ASoC: stm32: spdifrx: manage identification registers 

Add support of identification registers in STM32 SPDIFRX.

Signed-off-by: Olivier Moysan <olivier.moysan@st.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Olivier Moysan 2019-05-06 14:44:06 +02:00 committed by Mark Brown
parent b9960f6ea2
commit 1a5c0b28fc
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 35 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
sound/soc/stm/stm32_spdifrx.c
View File

@ -16,6 +16,7 @@
* details.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
@ -36,6 +37,9 @@
#define STM32_SPDIFRX_DR 0x10
#define STM32_SPDIFRX_CSR 0x14
#define STM32_SPDIFRX_DIR 0x18
#define STM32_SPDIFRX_VERR 0x3F4
#define STM32_SPDIFRX_IDR 0x3F8
#define STM32_SPDIFRX_SIDR 0x3FC
/* Bit definition for SPDIF_CR register */
#define SPDIFRX_CR_SPDIFEN_SHIFT 0
@ -169,6 +173,18 @@
#define SPDIFRX_SPDIFEN_SYNC 0x1
#define SPDIFRX_SPDIFEN_ENABLE 0x3
/* Bit definition for SPDIFRX_VERR register */
#define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0)
#define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4)
/* Bit definition for SPDIFRX_IDR register */
#define SPDIFRX_IDR_ID_MASK GENMASK(31, 0)
/* Bit definition for SPDIFRX_SIDR register */
#define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0)
#define SPDIFRX_IPIDR_NUMBER 0x00130041
#define SPDIFRX_IN1 0x1
#define SPDIFRX_IN2 0x2
#define SPDIFRX_IN3 0x3
@ -607,6 +623,9 @@ static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
case STM32_SPDIFRX_DR:
case STM32_SPDIFRX_CSR:
case STM32_SPDIFRX_DIR:
case STM32_SPDIFRX_VERR:
case STM32_SPDIFRX_IDR:
case STM32_SPDIFRX_SIDR:
return true;
default:
return false;
@ -642,10 +661,11 @@ static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = STM32_SPDIFRX_DIR,
.max_register = STM32_SPDIFRX_SIDR,
.readable_reg = stm32_spdifrx_readable_reg,
.volatile_reg = stm32_spdifrx_volatile_reg,
.writeable_reg = stm32_spdifrx_writeable_reg,
.num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1,
.fast_io = true,
.cache_type = REGCACHE_FLAT,
};
@ -911,6 +931,7 @@ static int stm32_spdifrx_probe(struct platform_device *pdev)
struct stm32_spdifrx_data *spdifrx;
struct reset_control *rst;
const struct snd_dmaengine_pcm_config *pcm_config = NULL;
u32 ver, idr;
int ret;
spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
@ -967,7 +988,19 @@ static int stm32_spdifrx_probe(struct platform_device *pdev)
goto error;
}
return 0;
ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr);
if (ret)
goto error;
if (idr == SPDIFRX_IPIDR_NUMBER) {
ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver);
dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n",
FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver),
FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver));
}
return ret;
error:
if (!IS_ERR(spdifrx->ctrl_chan))