drm/i915: Hook up Ivybridge eDP
The Ivybridge eDP control register looks like a cross between a Cougarpoint PCH DP control register and a Sandybridge eDP control register. Where things trivially match, share the code. Where there are any tricky bits, just split things out into two obviously separate code paths. Signed-off-by: Keith Packard <keithp@keithp.com> Tested-by: Fang Xun <xunx.fang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41991
This commit is contained in:
Keith Packard
parent
8d715f0024
commit
1a2eb4604b
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@ -3447,6 +3447,24 @@
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#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
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#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
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/* IVB */
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#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
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#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
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#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
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#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
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#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
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#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
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#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22)
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/* legacy values */
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#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
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#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
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#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
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#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
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#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
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#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
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#define FORCEWAKE 0xA18C
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#define FORCEWAKE_ACK 0x130090
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#define FORCEWAKE_MT 0xa188 /* multi-threaded */
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@ -362,8 +362,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
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* clock divider.
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*/
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if (is_cpu_edp(intel_dp)) {
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if (IS_GEN6(dev))
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aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
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if (IS_GEN6(dev) || IS_GEN7(dev))
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aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
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else
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aux_clock_divider = 225; /* eDP input clock at 450Mhz */
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} else if (HAS_PCH_SPLIT(dev))
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@ -817,10 +817,11 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
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}
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/*
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* There are three kinds of DP registers:
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* There are four kinds of DP registers:
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*
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* IBX PCH
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* CPU
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* SNB CPU
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* IVB CPU
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* CPT PCH
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*
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* IBX PCH and CPU are the same for almost everything,
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@ -873,7 +874,25 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
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/* Split out the IBX/CPU vs CPT settings */
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if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
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if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
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if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
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intel_dp->DP |= DP_SYNC_HS_HIGH;
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if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
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intel_dp->DP |= DP_SYNC_VS_HIGH;
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intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
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if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
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intel_dp->DP |= DP_ENHANCED_FRAMING;
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intel_dp->DP |= intel_crtc->pipe << 29;
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/* don't miss out required setting for eDP */
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intel_dp->DP |= DP_PLL_ENABLE;
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if (adjusted_mode->clock < 200000)
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intel_dp->DP |= DP_PLL_FREQ_160MHZ;
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else
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intel_dp->DP |= DP_PLL_FREQ_270MHZ;
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} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
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intel_dp->DP |= intel_dp->color_range;
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if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
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@ -1375,34 +1394,59 @@ static char *link_train_names[] = {
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* These are source-specific values; current Intel hardware supports
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* a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
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*/
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#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
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#define I830_DP_VOLTAGE_MAX_CPT DP_TRAIN_VOLTAGE_SWING_1200
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static uint8_t
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intel_dp_pre_emphasis_max(uint8_t voltage_swing)
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intel_dp_voltage_max(struct intel_dp *intel_dp)
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{
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switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_400:
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return DP_TRAIN_PRE_EMPHASIS_6;
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case DP_TRAIN_VOLTAGE_SWING_600:
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return DP_TRAIN_PRE_EMPHASIS_6;
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case DP_TRAIN_VOLTAGE_SWING_800:
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return DP_TRAIN_PRE_EMPHASIS_3_5;
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case DP_TRAIN_VOLTAGE_SWING_1200:
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default:
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return DP_TRAIN_PRE_EMPHASIS_0;
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struct drm_device *dev = intel_dp->base.base.dev;
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if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
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return DP_TRAIN_VOLTAGE_SWING_800;
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else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
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return DP_TRAIN_VOLTAGE_SWING_1200;
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else
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return DP_TRAIN_VOLTAGE_SWING_800;
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}
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static uint8_t
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intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
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{
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struct drm_device *dev = intel_dp->base.base.dev;
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if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
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switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_400:
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return DP_TRAIN_PRE_EMPHASIS_6;
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case DP_TRAIN_VOLTAGE_SWING_600:
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case DP_TRAIN_VOLTAGE_SWING_800:
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return DP_TRAIN_PRE_EMPHASIS_3_5;
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default:
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return DP_TRAIN_PRE_EMPHASIS_0;
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}
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} else {
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switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_400:
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return DP_TRAIN_PRE_EMPHASIS_6;
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case DP_TRAIN_VOLTAGE_SWING_600:
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return DP_TRAIN_PRE_EMPHASIS_6;
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case DP_TRAIN_VOLTAGE_SWING_800:
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return DP_TRAIN_PRE_EMPHASIS_3_5;
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case DP_TRAIN_VOLTAGE_SWING_1200:
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default:
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return DP_TRAIN_PRE_EMPHASIS_0;
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}
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}
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}
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static void
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intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
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{
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struct drm_device *dev = intel_dp->base.base.dev;
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uint8_t v = 0;
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uint8_t p = 0;
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int lane;
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uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
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int voltage_max;
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uint8_t voltage_max;
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uint8_t preemph_max;
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for (lane = 0; lane < intel_dp->lane_count; lane++) {
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uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
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@ -1414,15 +1458,13 @@ intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_ST
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p = this_p;
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}
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if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
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voltage_max = I830_DP_VOLTAGE_MAX_CPT;
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else
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voltage_max = I830_DP_VOLTAGE_MAX;
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voltage_max = intel_dp_voltage_max(intel_dp);
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if (v >= voltage_max)
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v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
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if (p >= intel_dp_pre_emphasis_max(v))
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p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
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if (p >= preemph_max)
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p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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for (lane = 0; lane < 4; lane++)
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intel_dp->train_set[lane] = v | p;
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@ -1494,6 +1536,37 @@ intel_gen6_edp_signal_levels(uint8_t train_set)
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}
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}
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/* Gen7's DP voltage swing and pre-emphasis control */
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static uint32_t
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intel_gen7_edp_signal_levels(uint8_t train_set)
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{
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int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
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DP_TRAIN_PRE_EMPHASIS_MASK);
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switch (signal_levels) {
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case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
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return EDP_LINK_TRAIN_400MV_0DB_IVB;
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case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
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return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
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case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
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return EDP_LINK_TRAIN_400MV_6DB_IVB;
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case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
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return EDP_LINK_TRAIN_600MV_0DB_IVB;
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case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
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return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
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case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
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return EDP_LINK_TRAIN_800MV_0DB_IVB;
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case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
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return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
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default:
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DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
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"0x%x\n", signal_levels);
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return EDP_LINK_TRAIN_500MV_0DB_IVB;
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}
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}
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static uint8_t
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intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
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int lane)
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@ -1599,7 +1672,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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DP_LINK_CONFIGURATION_SIZE);
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DP |= DP_PORT_EN;
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if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
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if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
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DP &= ~DP_LINK_TRAIN_MASK_CPT;
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else
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DP &= ~DP_LINK_TRAIN_MASK;
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@ -1613,7 +1687,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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uint8_t link_status[DP_LINK_STATUS_SIZE];
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uint32_t signal_levels;
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if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
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if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
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signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
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} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
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signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
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} else {
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@ -1622,7 +1700,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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}
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if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
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if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
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reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
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else
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reg = DP | DP_LINK_TRAIN_PAT_1;
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@ -1703,7 +1781,10 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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break;
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}
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if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
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if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
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signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
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} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
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signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
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} else {
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@ -1711,7 +1792,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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}
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if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
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if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
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reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
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else
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reg = DP | DP_LINK_TRAIN_PAT_2;
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@ -1752,7 +1833,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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++tries;
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}
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if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
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if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
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reg = DP | DP_LINK_TRAIN_OFF_CPT;
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else
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reg = DP | DP_LINK_TRAIN_OFF;
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@ -1782,7 +1863,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
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udelay(100);
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}
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if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) {
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if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
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DP &= ~DP_LINK_TRAIN_MASK_CPT;
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I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
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} else {
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@ -1794,7 +1875,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
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msleep(17);
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if (is_edp(intel_dp)) {
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if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
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if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
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DP |= DP_LINK_TRAIN_OFF_CPT;
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else
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DP |= DP_LINK_TRAIN_OFF;
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