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linux-can-next-for-5.10-20200923 

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Merge tag 'linux-can-next-for-5.10-20200923' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next

Marc Kleine-Budde says:

====================
pull-request: can-next 2020-09-23

this is a pull request of 20 patches for net-next.

The complete series target the flexcan driver and is created by Joakim
Zhang and me.

The first six patches are cleanup (sort include files alphabetically,
remove stray empty line, get rid of long lines) and adding more
registers and documentation (registers and wakeup interrupt).

Then in two patches the transceiver regulator is made optional, and a
check for maximum transceiver bitrate is added.

Then the ECC support for HW thats supports this is added.

The next three patches improve suspend and low power mode handling.

Followed by six patches that add CAN-FD support and CAN-FD related
features.

The last two patches add support for the flexcan IP core on the imx8qm
and lx2160ar1.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2020-09-23 12:09:08 -07:00
parent 40fe2e0db7 2c19bb43e5
commit 1a26e88d53
1 changed files with 443 additions and 90 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

533
drivers/net/can/flexcan.c
View File

@ -9,7 +9,7 @@
//
// Based on code originally by Andrey Volkov <avolkov@varma-el.com>
#include <linux/netdevice.h>
#include <linux/bitfield.h>
#include <linux/can.h>
#include <linux/can/dev.h>
#include <linux/can/error.h>
@ -21,12 +21,14 @@
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#define DRV_NAME "flexcan"
@ -52,6 +54,7 @@
#define FLEXCAN_MCR_IRMQ BIT(16)
#define FLEXCAN_MCR_LPRIO_EN BIT(13)
#define FLEXCAN_MCR_AEN BIT(12)
#define FLEXCAN_MCR_FDEN BIT(11)
/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
#define FLEXCAN_MCR_IDAM_A (0x0 << 8)
@ -91,6 +94,7 @@
#define FLEXCAN_CTRL2_MRP BIT(18)
#define FLEXCAN_CTRL2_RRS BIT(17)
#define FLEXCAN_CTRL2_EACEN BIT(16)
#define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
/* FLEXCAN memory error control register (MECR) bits */
#define FLEXCAN_MECR_ECRWRDIS BIT(31)
@ -134,8 +138,35 @@
(FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
#define FLEXCAN_ESR_ALL_INT \
(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
FLEXCAN_ESR_WAK_INT)
FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
/* FLEXCAN Bit Timing register (CBT) bits */
#define FLEXCAN_CBT_BTF BIT(31)
#define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21)
#define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16)
#define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10)
#define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5)
#define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)
/* FLEXCAN FD control register (FDCTRL) bits */
#define FLEXCAN_FDCTRL_FDRATE BIT(31)
#define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19)
#define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16)
#define FLEXCAN_FDCTRL_MBDSR_8 0x0
#define FLEXCAN_FDCTRL_MBDSR_12 0x1
#define FLEXCAN_FDCTRL_MBDSR_32 0x2
#define FLEXCAN_FDCTRL_MBDSR_64 0x3
#define FLEXCAN_FDCTRL_TDCEN BIT(15)
#define FLEXCAN_FDCTRL_TDCFAIL BIT(14)
#define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8)
#define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)
/* FLEXCAN FD Bit Timing register (FDCBT) bits */
#define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20)
#define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16)
#define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10)
#define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5)
#define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)
/* FLEXCAN interrupt flag register (IFLAG) bits */
/* Errata ERR005829 step7: Reserve first valid MB */
@ -161,6 +192,9 @@
#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
#define FLEXCAN_MB_CNT_EDL BIT(31)
#define FLEXCAN_MB_CNT_BRS BIT(30)
#define FLEXCAN_MB_CNT_ESI BIT(29)
#define FLEXCAN_MB_CNT_SRR BIT(22)
#define FLEXCAN_MB_CNT_IDE BIT(21)
#define FLEXCAN_MB_CNT_RTR BIT(20)
@ -172,26 +206,39 @@
/* FLEXCAN hardware feature flags
*
* Below is some version info we got:
* SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
* Filter? connected? Passive detection ception in MB
* MX25 FlexCAN2 03.00.00.00 no no no no no
* MX28 FlexCAN2 03.00.04.00 yes yes no no no
* MX35 FlexCAN2 03.00.00.00 no no no no no
* MX53 FlexCAN2 03.00.00.00 yes no no no no
* MX6s FlexCAN3 10.00.12.00 yes yes no no yes
* VF610 FlexCAN3 ? no yes no yes yes?
* LS1021A FlexCAN2 03.00.04.00 no yes no no yes
* SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode
* Filter? connected? Passive detection ption in MB Supported?
* MX25 FlexCAN2 03.00.00.00 no no no no no no
* MX28 FlexCAN2 03.00.04.00 yes yes no no no no
* MX35 FlexCAN2 03.00.00.00 no no no no no no
* MX53 FlexCAN2 03.00.00.00 yes no no no no no
* MX6s FlexCAN3 10.00.12.00 yes yes no no yes no
* MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes
* VF610 FlexCAN3 ? no yes no yes yes? no
* LS1021A FlexCAN2 03.00.04.00 no yes no no yes no
* LX2160A FlexCAN3 03.00.23.00 no yes no no yes yes
*
* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
*/
#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7) /* default to BE register access */
#define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8) /* Setup stop mode to support wakeup */
/* [TR]WRN_INT not connected */
#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
/* Disable RX FIFO Global mask */
#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
/* Enable EACEN and RRS bit in ctrl2 */
#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
/* Disable non-correctable errors interrupt and freeze mode */
#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
/* Use timestamp based offloading */
#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
/* No interrupt for error passive */
#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
/* default to BE register access */
#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
/* Setup stop mode to support wakeup */
#define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8)
/* Support CAN-FD mode */
#define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
/* Structure of the message buffer */
struct flexcan_mb {
@ -203,12 +250,12 @@ struct flexcan_mb {
/* Structure of the hardware registers */
struct flexcan_regs {
u32 mcr; /* 0x00 */
u32 ctrl; /* 0x04 */
u32 ctrl; /* 0x04 - Not affected by Soft Reset */
u32 timer; /* 0x08 */
u32 _reserved1; /* 0x0c */
u32 rxgmask; /* 0x10 */
u32 rx14mask; /* 0x14 */
u32 rx15mask; /* 0x18 */
u32 tcr; /* 0x0c */
u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
u32 ecr; /* 0x1c */
u32 esr; /* 0x20 */
u32 imask2; /* 0x24 */
@ -217,16 +264,20 @@ struct flexcan_regs {
u32 iflag1; /* 0x30 */
union { /* 0x34 */
u32 gfwr_mx28; /* MX28, MX53 */
u32 ctrl2; /* MX6, VF610 */
u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
};
u32 esr2; /* 0x38 */
u32 imeur; /* 0x3c */
u32 lrfr; /* 0x40 */
u32 crcr; /* 0x44 */
u32 rxfgmask; /* 0x48 */
u32 rxfir; /* 0x4c */
u32 _reserved3[12]; /* 0x50 */
u8 mb[2][512]; /* 0x80 */
u32 rxfir; /* 0x4c - Not affected by Soft Reset */
u32 cbt; /* 0x50 - Not affected by Soft Reset */
u32 _reserved2; /* 0x54 */
u32 dbg1; /* 0x58 */
u32 dbg2; /* 0x5c */
u32 _reserved3[8]; /* 0x60 */
u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
/* FIFO-mode:
* MB
* 0x080...0x08f 0 RX message buffer
@ -238,7 +289,7 @@ struct flexcan_regs {
* (mx6, vf610)
*/
u32 _reserved4[256]; /* 0x480 */
u32 rximr[64]; /* 0x880 */
u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
u32 _reserved5[24]; /* 0x980 */
u32 gfwr_mx6; /* 0x9e0 - MX6 */
u32 _reserved6[63]; /* 0x9e4 */
@ -250,8 +301,14 @@ struct flexcan_regs {
u32 rerrdr; /* 0xaf4 */
u32 rerrsynr; /* 0xaf8 */
u32 errsr; /* 0xafc */
u32 _reserved7[64]; /* 0xb00 */
u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
u32 fdcrc; /* 0xc08 */
};
static_assert(sizeof(struct flexcan_regs) == 0x4 + 0xc08);
struct flexcan_devtype_data {
u32 quirks; /* quirks needed for different IP cores */
};
@ -313,6 +370,12 @@ static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
FLEXCAN_QUIRK_SETUP_STOP_MODE,
};
static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
FLEXCAN_QUIRK_SUPPORT_FD,
};
static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
@ -325,6 +388,12 @@ static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
};
static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD,
};
static const struct can_bittiming_const flexcan_bittiming_const = {
.name = DRV_NAME,
.tseg1_min = 4,
@ -337,6 +406,30 @@ static const struct can_bittiming_const flexcan_bittiming_const = {
.brp_inc = 1,
};
static const struct can_bittiming_const flexcan_fd_bittiming_const = {
.name = DRV_NAME,
.tseg1_min = 2,
.tseg1_max = 96,
.tseg2_min = 2,
.tseg2_max = 32,
.sjw_max = 16,
.brp_min = 1,
.brp_max = 1024,
.brp_inc = 1,
};
static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
.name = DRV_NAME,
.tseg1_min = 2,
.tseg1_max = 39,
.tseg2_min = 2,
.tseg2_max = 8,
.sjw_max = 4,
.brp_min = 1,
.brp_max = 1024,
.brp_inc = 1,
};
/* FlexCAN module is essentially modelled as a little-endian IP in most
* SoCs, i.e the registers as well as the message buffer areas are
* implemented in a little-endian fashion.
@ -457,7 +550,6 @@ static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
1 << priv->stm.req_bit, 0);
reg_mcr = priv->read(&regs->mcr);
reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
priv->write(reg_mcr, &regs->mcr);
@ -628,10 +720,10 @@ static int flexcan_get_berr_counter(const struct net_device *dev,
static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
const struct flexcan_priv *priv = netdev_priv(dev);
struct can_frame *cf = (struct can_frame *)skb->data;
struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
u32 can_id;
u32 data;
u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_len2dlc(cfd->len)) << 16);
int i;
if (can_dropped_invalid_skb(dev, skb))
@ -639,18 +731,25 @@ static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *de
netif_stop_queue(dev);
if (cf->can_id & CAN_EFF_FLAG) {
can_id = cf->can_id & CAN_EFF_MASK;
if (cfd->can_id & CAN_EFF_FLAG) {
can_id = cfd->can_id & CAN_EFF_MASK;
ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
} else {
can_id = (cf->can_id & CAN_SFF_MASK) << 18;
can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
}
if (cf->can_id & CAN_RTR_FLAG)
if (cfd->can_id & CAN_RTR_FLAG)
ctrl |= FLEXCAN_MB_CNT_RTR;
for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
data = be32_to_cpup((__be32 *)&cf->data[i]);
if (can_is_canfd_skb(skb)) {
ctrl |= FLEXCAN_MB_CNT_EDL;
if (cfd->flags & CANFD_BRS)
ctrl |= FLEXCAN_MB_CNT_BRS;
}
for (i = 0; i < cfd->len; i += sizeof(u32)) {
data = be32_to_cpup((__be32 *)&cfd->data[i]);
priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
}
@ -822,7 +921,7 @@ static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
struct flexcan_regs __iomem *regs = priv->regs;
struct flexcan_mb __iomem *mb;
struct sk_buff *skb;
struct can_frame *cf;
struct canfd_frame *cfd;
u32 reg_ctrl, reg_id, reg_iflag1;
int i;
@ -859,8 +958,11 @@ static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
reg_ctrl = priv->read(&mb->can_ctrl);
}
skb = alloc_can_skb(offload->dev, &cf);
if (!skb) {
if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
skb = alloc_canfd_skb(offload->dev, &cfd);
else
skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
if (unlikely(!skb)) {
skb = ERR_PTR(-ENOMEM);
goto mark_as_read;
}
@ -870,17 +972,28 @@ static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
reg_id = priv->read(&mb->can_id);
if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
else
cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
cf->can_id |= CAN_RTR_FLAG;
cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
cfd->len = can_dlc2len(get_canfd_dlc((reg_ctrl >> 16) & 0xf));
for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
cfd->flags |= CANFD_BRS;
} else {
cfd->len = get_can_dlc((reg_ctrl >> 16) & 0xf);
if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
cfd->can_id |= CAN_RTR_FLAG;
}
if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
cfd->flags |= CANFD_ESI;
for (i = 0; i < cfd->len; i += sizeof(u32)) {
__be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
*(__be32 *)(cf->data + i) = data;
*(__be32 *)(cfd->data + i) = data;
}
mark_as_read:
@ -961,10 +1074,10 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
reg_esr = priv->read(&regs->esr);
/* ACK all bus error and state change IRQ sources */
if (reg_esr & FLEXCAN_ESR_ALL_INT) {
/* ACK all bus error, state change and wake IRQ sources */
if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
handled = IRQ_HANDLED;
priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), &regs->esr);
}
/* state change interrupt or broken error state quirk fix is enabled */
@ -1019,7 +1132,7 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
return handled;
}
static void flexcan_set_bittiming(struct net_device *dev)
static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
{
const struct flexcan_priv *priv = netdev_priv(dev);
const struct can_bittiming *bt = &priv->can.bittiming;
@ -1031,10 +1144,7 @@ static void flexcan_set_bittiming(struct net_device *dev)
FLEXCAN_CTRL_RJW(0x3) |
FLEXCAN_CTRL_PSEG1(0x7) |
FLEXCAN_CTRL_PSEG2(0x7) |
FLEXCAN_CTRL_PROPSEG(0x7) |
FLEXCAN_CTRL_LPB |
FLEXCAN_CTRL_SMP |
FLEXCAN_CTRL_LOM);
FLEXCAN_CTRL_PROPSEG(0x7));
reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
@ -1042,6 +1152,130 @@ static void flexcan_set_bittiming(struct net_device *dev)
FLEXCAN_CTRL_RJW(bt->sjw - 1) |
FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
priv->write(reg, &regs->ctrl);
/* print chip status */
netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
priv->read(&regs->mcr), priv->read(&regs->ctrl));
}
static void flexcan_set_bittiming_cbt(const struct net_device *dev)
{
struct flexcan_priv *priv = netdev_priv(dev);
struct can_bittiming *bt = &priv->can.bittiming;
struct can_bittiming *dbt = &priv->can.data_bittiming;
struct flexcan_regs __iomem *regs = priv->regs;
u32 reg_cbt, reg_fdctrl;
/* CBT */
/* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
* long. The can_calc_bittiming() tries to divide the tseg1
* equally between phase_seg1 and prop_seg, which may not fit
* in CBT register. Therefore, if phase_seg1 is more than
* possible value, increase prop_seg and decrease phase_seg1.
*/
if (bt->phase_seg1 > 0x20) {
bt->prop_seg += (bt->phase_seg1 - 0x20);
bt->phase_seg1 = 0x20;
}
reg_cbt = FLEXCAN_CBT_BTF |
FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
priv->write(reg_cbt, &regs->cbt);
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
u32 reg_fdcbt, reg_ctrl2;
if (bt->brp != dbt->brp)
netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
dbt->brp, bt->brp);
/* FDCBT */
/* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
* 5 bit long. The can_calc_bittiming tries to divide
* the tseg1 equally between phase_seg1 and prop_seg,
* which may not fit in FDCBT register. Therefore, if
* phase_seg1 is more than possible value, increase
* prop_seg and decrease phase_seg1
*/
if (dbt->phase_seg1 > 0x8) {
dbt->prop_seg += (dbt->phase_seg1 - 0x8);
dbt->phase_seg1 = 0x8;
}
reg_fdcbt = priv->read(&regs->fdcbt);
reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
priv->write(reg_fdcbt, &regs->fdcbt);
/* CTRL2 */
reg_ctrl2 = priv->read(&regs->ctrl2);
reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
priv->write(reg_ctrl2, &regs->ctrl2);
}
/* FDCTRL */
reg_fdctrl = priv->read(&regs->fdctrl);
reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
/* TDC must be disabled for Loop Back mode */
reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
} else {
reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
((dbt->phase_seg1 - 1) +
dbt->prop_seg + 2) *
((dbt->brp - 1 ) + 1));
}
}
netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
priv->write(reg_fdctrl, &regs->fdctrl);
netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
__func__,
priv->read(&regs->mcr), priv->read(&regs->ctrl),
priv->read(&regs->ctrl2), priv->read(&regs->fdctrl),
priv->read(&regs->cbt), priv->read(&regs->fdcbt));
}
static void flexcan_set_bittiming(struct net_device *dev)
{
const struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->regs;
u32 reg;
reg = priv->read(&regs->ctrl);
reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
FLEXCAN_CTRL_LOM);
if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
reg |= FLEXCAN_CTRL_LPB;
if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
@ -1052,9 +1286,10 @@ static void flexcan_set_bittiming(struct net_device *dev)
netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
priv->write(reg, &regs->ctrl);
/* print chip status */
netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
priv->read(&regs->mcr), priv->read(&regs->ctrl));
if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
return flexcan_set_bittiming_cbt(dev);
else
return flexcan_set_bittiming_ctrl(dev);
}
/* flexcan_chip_start
@ -1127,6 +1362,12 @@ static int flexcan_chip_start(struct net_device *dev)
else
reg_mcr |= FLEXCAN_MCR_SRX_DIS;
/* MCR - CAN-FD */
if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
reg_mcr |= FLEXCAN_MCR_FDEN;
else
reg_mcr &= ~FLEXCAN_MCR_FDEN;
netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
priv->write(reg_mcr, &regs->mcr);
@ -1169,6 +1410,32 @@ static int flexcan_chip_start(struct net_device *dev)
priv->write(reg_ctrl2, &regs->ctrl2);
}
if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
u32 reg_fdctrl;
reg_fdctrl = priv->read(&regs->fdctrl);
reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
reg_fdctrl |=
FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
FLEXCAN_FDCTRL_MBDSR_64) |
FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
FLEXCAN_FDCTRL_MBDSR_64);
} else {
reg_fdctrl |=
FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
FLEXCAN_FDCTRL_MBDSR_8) |
FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
FLEXCAN_FDCTRL_MBDSR_8);
}
netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
__func__, reg_fdctrl);
priv->write(reg_fdctrl, &regs->fdctrl);
}
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
mb = flexcan_get_mb(priv, i);
@ -1204,28 +1471,43 @@ static int flexcan_chip_start(struct net_device *dev)
for (i = 0; i < priv->mb_count; i++)
priv->write(0, &regs->rximr[i]);
/* On Vybrid, disable memory error detection interrupts
* and freeze mode.
* This also works around errata e5295 which generates
* false positive memory errors and put the device in
* freeze mode.
/* On Vybrid, disable non-correctable errors interrupt and
* freeze mode. It still can correct the correctable errors
* when HW supports ECC.
*
* This also works around errata e5295 which generates false
* positive memory errors and put the device in freeze mode.
*/
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
/* Follow the protocol as described in "Detection
* and Correction of Memory Errors" to write to
* MECR register
* MECR register (step 1 - 5)
*
* 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
* 2. set CTRL2[ECRWRE]
*/
reg_ctrl2 = priv->read(&regs->ctrl2);
reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
priv->write(reg_ctrl2, &regs->ctrl2);
/* 3. clear MECR[ECRWRDIS] */
reg_mecr = priv->read(&regs->mecr);
reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
priv->write(reg_mecr, &regs->mecr);
reg_mecr |= FLEXCAN_MECR_ECCDIS;
/* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
FLEXCAN_MECR_FANCEI_MSK);
priv->write(reg_mecr, &regs->mecr);
/* 5. after configuration done, lock MECR by either
* setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
*/
reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
priv->write(reg_mecr, &regs->mecr);
reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
priv->write(reg_ctrl2, &regs->ctrl2);
}
err = flexcan_transceiver_enable(priv);
@ -1260,18 +1542,23 @@ static int flexcan_chip_start(struct net_device *dev)
return err;
}
/* flexcan_chip_stop
/* __flexcan_chip_stop
*
* this functions is entered with clocks enabled
* this function is entered with clocks enabled
*/
static void flexcan_chip_stop(struct net_device *dev)
static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
{
struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->regs;
int err;
/* freeze + disable module */
flexcan_chip_freeze(priv);
flexcan_chip_disable(priv);
err = flexcan_chip_freeze(priv);
if (err && !disable_on_error)
return err;
err = flexcan_chip_disable(priv);
if (err && !disable_on_error)
goto out_chip_unfreeze;
/* Disable all interrupts */
priv->write(0, &regs->imask2);
@ -1281,6 +1568,23 @@ static void flexcan_chip_stop(struct net_device *dev)
flexcan_transceiver_disable(priv);
priv->can.state = CAN_STATE_STOPPED;
return 0;
out_chip_unfreeze:
flexcan_chip_unfreeze(priv);
return err;
}
static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
{
return __flexcan_chip_stop(dev, true);
}
static inline int flexcan_chip_stop(struct net_device *dev)
{
return __flexcan_chip_stop(dev, false);
}
static int flexcan_open(struct net_device *dev)
@ -1288,6 +1592,12 @@ static int flexcan_open(struct net_device *dev)
struct flexcan_priv *priv = netdev_priv(dev);
int err;
if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
return -EINVAL;
}
err = pm_runtime_get_sync(priv->dev);
if (err < 0)
return err;
@ -1300,7 +1610,10 @@ static int flexcan_open(struct net_device *dev)
if (err)
goto out_close;
priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
else
priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
(sizeof(priv->regs->mb[1]) / priv->mb_size);
@ -1362,7 +1675,7 @@ static int flexcan_close(struct net_device *dev)
netif_stop_queue(dev);
can_rx_offload_disable(&priv->offload);
flexcan_chip_stop(dev);
flexcan_chip_stop_disable_on_error(dev);
can_rx_offload_del(&priv->offload);
free_irq(dev->irq, dev);
@ -1531,6 +1844,7 @@ out_put_node:
}
static const struct of_device_id flexcan_of_match[] = {
{ .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
{ .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
@ -1539,6 +1853,7 @@ static const struct of_device_id flexcan_of_match[] = {
{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
{ .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, flexcan_of_match);
@ -1562,11 +1877,13 @@ static int flexcan_probe(struct platform_device *pdev)
u8 clk_src = 1;
u32 clock_freq = 0;
reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
return -EPROBE_DEFER;
else if (IS_ERR(reg_xceiver))
else if (PTR_ERR(reg_xceiver) == -ENODEV)
reg_xceiver = NULL;
else if (IS_ERR(reg_xceiver))
return PTR_ERR(reg_xceiver);
if (pdev->dev.of_node) {
of_property_read_u32(pdev->dev.of_node,
@ -1608,6 +1925,12 @@ static int flexcan_probe(struct platform_device *pdev)
return -ENODEV;
}
if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
!(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) {
dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n");
return -EINVAL;
}
dev = alloc_candev(sizeof(struct flexcan_priv), 1);
if (!dev)
return -ENOMEM;
@ -1632,7 +1955,6 @@ static int flexcan_probe(struct platform_device *pdev)
priv->dev = &pdev->dev;
priv->can.clock.freq = clock_freq;
priv->can.bittiming_const = &flexcan_bittiming_const;
priv->can.do_set_mode = flexcan_set_mode;
priv->can.do_get_berr_counter = flexcan_get_berr_counter;
priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
@ -1645,6 +1967,16 @@ static int flexcan_probe(struct platform_device *pdev)
priv->devtype_data = devtype_data;
priv->reg_xceiver = reg_xceiver;
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
CAN_CTRLMODE_FD_NON_ISO;
priv->can.bittiming_const = &flexcan_fd_bittiming_const;
priv->can.data_bittiming_const =
&flexcan_fd_data_bittiming_const;
} else {
priv->can.bittiming_const = &flexcan_bittiming_const;
}
pm_runtime_get_noresume(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
@ -1655,6 +1987,7 @@ static int flexcan_probe(struct platform_device *pdev)
goto failed_register;
}
of_can_transceiver(dev);
devm_can_led_init(dev);
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
@ -1685,7 +2018,7 @@ static int __maybe_unused flexcan_suspend(struct device *device)
{
struct net_device *dev = dev_get_drvdata(device);
struct flexcan_priv *priv = netdev_priv(dev);
int err = 0;
int err;
if (netif_running(dev)) {
/* if wakeup is enabled, enter stop mode
@ -1697,25 +2030,27 @@ static int __maybe_unused flexcan_suspend(struct device *device)
if (err)
return err;
} else {
err = flexcan_chip_disable(priv);
err = flexcan_chip_stop(dev);
if (err)
return err;
err = pm_runtime_force_suspend(device);
err = pinctrl_pm_select_sleep_state(device);
if (err)
return err;
}
netif_stop_queue(dev);
netif_device_detach(dev);
}
priv->can.state = CAN_STATE_SLEEPING;
return err;
return 0;
}
static int __maybe_unused flexcan_resume(struct device *device)
{
struct net_device *dev = dev_get_drvdata(device);
struct flexcan_priv *priv = netdev_priv(dev);
int err = 0;
int err;
priv->can.state = CAN_STATE_ERROR_ACTIVE;
if (netif_running(dev)) {
@ -1727,15 +2062,17 @@ static int __maybe_unused flexcan_resume(struct device *device)
if (err)
return err;
} else {
err = pm_runtime_force_resume(device);
err = pinctrl_pm_select_default_state(device);
if (err)
return err;
err = flexcan_chip_enable(priv);
err = flexcan_chip_start(dev);
if (err)
return err;
}
}
return err;
return 0;
}
static int __maybe_unused flexcan_runtime_suspend(struct device *device)
@ -1761,8 +2098,16 @@ static int __maybe_unused flexcan_noirq_suspend(struct device *device)
struct net_device *dev = dev_get_drvdata(device);
struct flexcan_priv *priv = netdev_priv(dev);
if (netif_running(dev) && device_may_wakeup(device))
flexcan_enable_wakeup_irq(priv, true);
if (netif_running(dev)) {
int err;
if (device_may_wakeup(device))
flexcan_enable_wakeup_irq(priv, true);
err = pm_runtime_force_suspend(device);
if (err)
return err;
}
return 0;
}
@ -1772,8 +2117,16 @@ static int __maybe_unused flexcan_noirq_resume(struct device *device)
struct net_device *dev = dev_get_drvdata(device);
struct flexcan_priv *priv = netdev_priv(dev);
if (netif_running(dev) && device_may_wakeup(device))
flexcan_enable_wakeup_irq(priv, false);
if (netif_running(dev)) {
int err;
err = pm_runtime_force_resume(device);
if (err)
return err;
if (device_may_wakeup(device))
flexcan_enable_wakeup_irq(priv, false);
}
return 0;
}