LoongArch: Add alternative runtime patching mechanism
Introduce the "alternative" mechanism from ARM64 and x86 for LoongArch to apply runtime patching. The main purpose of this patch is to provide a framework. In future we can use this mechanism (i.e., the ALTERNATIVE and ALTERNATIVE_2 macros) to optimize hotspot functions according to cpu features. Signed-off-by: Jun Yi <yijun@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Huacai Chen
parent
61a6fccc0b
commit
19e5eb15b0
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@ -0,0 +1,82 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_ALTERNATIVE_ASM_H
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#define _ASM_ALTERNATIVE_ASM_H
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#ifdef __ASSEMBLY__
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#include <asm/asm.h>
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/*
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* Issue one struct alt_instr descriptor entry (need to put it into
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* the section .altinstructions, see below). This entry contains
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* enough information for the alternatives patching code to patch an
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* instruction. See apply_alternatives().
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*/
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.macro altinstruction_entry orig alt feature orig_len alt_len
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.long \orig - .
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.long \alt - .
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.short \feature
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.byte \orig_len
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.byte \alt_len
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.endm
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/*
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* Define an alternative between two instructions. If @feature is
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* present, early code in apply_alternatives() replaces @oldinstr with
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* @newinstr. ".fill" directive takes care of proper instruction padding
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* in case @newinstr is longer than @oldinstr.
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*/
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.macro ALTERNATIVE oldinstr, newinstr, feature
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140 :
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\oldinstr
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141 :
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.fill - (((144f-143f)-(141b-140b)) > 0) * ((144f-143f)-(141b-140b)) / 4, 4, 0x03400000
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142 :
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.pushsection .altinstructions, "a"
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altinstruction_entry 140b, 143f, \feature, 142b-140b, 144f-143f
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.popsection
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.subsection 1
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143 :
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\newinstr
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144 :
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.previous
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.endm
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#define old_len (141b-140b)
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#define new_len1 (144f-143f)
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#define new_len2 (145f-144f)
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#define alt_max_short(a, b) ((a) ^ (((a) ^ (b)) & -(-((a) < (b)))))
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/*
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* Same as ALTERNATIVE macro above but for two alternatives. If CPU
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* has @feature1, it replaces @oldinstr with @newinstr1. If CPU has
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* @feature2, it replaces @oldinstr with @feature2.
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*/
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.macro ALTERNATIVE_2 oldinstr, newinstr1, feature1, newinstr2, feature2
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140 :
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\oldinstr
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141 :
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.fill - ((alt_max_short(new_len1, new_len2) - (old_len)) > 0) * \
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(alt_max_short(new_len1, new_len2) - (old_len)) / 4, 4, 0x03400000
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142 :
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.pushsection .altinstructions, "a"
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altinstruction_entry 140b, 143f, \feature1, 142b-140b, 144f-143f, 142b-141b
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altinstruction_entry 140b, 144f, \feature2, 142b-140b, 145f-144f, 142b-141b
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.popsection
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.subsection 1
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143 :
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\newinstr1
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144 :
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\newinstr2
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145 :
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.previous
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ALTERNATIVE_ASM_H */
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@ -0,0 +1,111 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_ALTERNATIVE_H
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#define _ASM_ALTERNATIVE_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/stddef.h>
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#include <linux/stringify.h>
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#include <asm/asm.h>
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struct alt_instr {
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s32 instr_offset; /* offset to original instruction */
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s32 replace_offset; /* offset to replacement instruction */
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u16 feature; /* feature bit set for replacement */
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u8 instrlen; /* length of original instruction */
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u8 replacementlen; /* length of new instruction */
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} __packed;
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/*
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* Debug flag that can be tested to see whether alternative
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* instructions were patched in already:
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*/
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extern int alternatives_patched;
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extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
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extern void alternative_instructions(void);
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extern void apply_alternatives(struct alt_instr *start, struct alt_instr *end);
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#define b_replacement(num) "664"#num
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#define e_replacement(num) "665"#num
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#define alt_end_marker "663"
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#define alt_slen "662b-661b"
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#define alt_total_slen alt_end_marker"b-661b"
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#define alt_rlen(num) e_replacement(num)"f-"b_replacement(num)"f"
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#define __OLDINSTR(oldinstr, num) \
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"661:\n\t" oldinstr "\n662:\n" \
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".fill -(((" alt_rlen(num) ")-(" alt_slen ")) > 0) * " \
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"((" alt_rlen(num) ")-(" alt_slen ")) / 4, 4, 0x03400000\n"
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#define OLDINSTR(oldinstr, num) \
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__OLDINSTR(oldinstr, num) \
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alt_end_marker ":\n"
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#define alt_max_short(a, b) "((" a ") ^ (((" a ") ^ (" b ")) & -(-((" a ") < (" b ")))))"
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/*
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* Pad the second replacement alternative with additional NOPs if it is
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* additionally longer than the first replacement alternative.
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*/
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#define OLDINSTR_2(oldinstr, num1, num2) \
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"661:\n\t" oldinstr "\n662:\n" \
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".fill -((" alt_max_short(alt_rlen(num1), alt_rlen(num2)) " - (" alt_slen ")) > 0) * " \
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"(" alt_max_short(alt_rlen(num1), alt_rlen(num2)) " - (" alt_slen ")) / 4, " \
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"4, 0x03400000\n" \
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alt_end_marker ":\n"
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#define ALTINSTR_ENTRY(feature, num) \
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" .long 661b - .\n" /* label */ \
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" .long " b_replacement(num)"f - .\n" /* new instruction */ \
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" .short " __stringify(feature) "\n" /* feature bit */ \
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" .byte " alt_total_slen "\n" /* source len */ \
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" .byte " alt_rlen(num) "\n" /* replacement len */
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#define ALTINSTR_REPLACEMENT(newinstr, feature, num) /* replacement */ \
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b_replacement(num)":\n\t" newinstr "\n" e_replacement(num) ":\n\t"
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/* alternative assembly primitive: */
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#define ALTERNATIVE(oldinstr, newinstr, feature) \
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OLDINSTR(oldinstr, 1) \
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".pushsection .altinstructions,\"a\"\n" \
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ALTINSTR_ENTRY(feature, 1) \
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".popsection\n" \
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".subsection 1\n" \
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ALTINSTR_REPLACEMENT(newinstr, feature, 1) \
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".previous\n"
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#define ALTERNATIVE_2(oldinstr, newinstr1, feature1, newinstr2, feature2)\
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OLDINSTR_2(oldinstr, 1, 2) \
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".pushsection .altinstructions,\"a\"\n" \
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ALTINSTR_ENTRY(feature1, 1) \
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ALTINSTR_ENTRY(feature2, 2) \
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".popsection\n" \
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".subsection 1\n" \
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ALTINSTR_REPLACEMENT(newinstr1, feature1, 1) \
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ALTINSTR_REPLACEMENT(newinstr2, feature2, 2) \
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".previous\n"
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/*
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* Alternative instructions for different CPU types or capabilities.
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*
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* This allows to use optimized instructions even on generic binary
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* kernels.
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*
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* length of oldinstr must be longer or equal the length of newinstr
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* It can be padded with nops as needed.
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*
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* For non barrier like inlines please define new variants
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* without volatile and memory clobber.
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*/
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#define alternative(oldinstr, newinstr, feature) \
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(asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) : : : "memory"))
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#define alternative_2(oldinstr, newinstr1, feature1, newinstr2, feature2) \
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(asm volatile(ALTERNATIVE_2(oldinstr, newinstr1, feature1, newinstr2, feature2) ::: "memory"))
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ALTERNATIVE_H */
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@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This is included by init/main.c to check for architecture-dependent bugs.
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_BUGS_H
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#define _ASM_BUGS_H
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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extern void check_bugs(void);
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#endif /* _ASM_BUGS_H */
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@ -8,6 +8,7 @@
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#include <linux/types.h>
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#include <asm/asm.h>
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#define INSN_NOP 0x03400000
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#define INSN_BREAK 0x002a0000
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#define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
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@ -28,6 +29,7 @@ enum reg0i26_op {
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enum reg1i20_op {
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lu12iw_op = 0x0a,
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lu32id_op = 0x0b,
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pcaddi_op = 0x0c,
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pcaddu12i_op = 0x0e,
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pcaddu18i_op = 0x0f,
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};
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@ -35,6 +37,8 @@ enum reg1i20_op {
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enum reg1i21_op {
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beqz_op = 0x10,
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bnez_op = 0x11,
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bceqz_op = 0x12, /* bits[9:8] = 0x00 */
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bcnez_op = 0x12, /* bits[9:8] = 0x01 */
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};
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enum reg2_op {
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@ -315,6 +319,12 @@ static inline bool is_imm_negative(unsigned long val, unsigned int bit)
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return val & (1UL << (bit - 1));
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}
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static inline bool is_pc_ins(union loongarch_instruction *ip)
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{
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return ip->reg1i20_format.opcode >= pcaddi_op &&
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ip->reg1i20_format.opcode <= pcaddu18i_op;
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}
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static inline bool is_branch_ins(union loongarch_instruction *ip)
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{
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return ip->reg1i21_format.opcode >= beqz_op &&
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@ -353,6 +363,14 @@ static inline bool unsigned_imm_check(unsigned long val, unsigned int bit)
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return val < (1UL << bit);
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}
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static inline unsigned long sign_extend(unsigned long val, unsigned int idx)
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{
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if (!is_imm_negative(val, idx + 1))
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return ((1UL << idx) - 1) & val;
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else
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return ~((1UL << idx) - 1) | val;
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}
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#define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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int offset) \
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@ -8,7 +8,7 @@ extra-y := vmlinux.lds
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obj-y += head.o cpu-probe.o cacheinfo.o env.o setup.o entry.o genex.o \
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traps.o irq.o idle.o process.o dma.o mem.o io.o reset.o switch.o \
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elf.o syscall.o signal.o time.o topology.o inst.o ptrace.o vdso.o \
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unaligned.o
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alternative.o unaligned.o
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obj-$(CONFIG_ACPI) += acpi.o
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obj-$(CONFIG_EFI) += efi.o
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@ -0,0 +1,246 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <asm/alternative.h>
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#include <asm/cacheflush.h>
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#include <asm/inst.h>
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#include <asm/sections.h>
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int __read_mostly alternatives_patched;
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EXPORT_SYMBOL_GPL(alternatives_patched);
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#define MAX_PATCH_SIZE (((u8)(-1)) / LOONGARCH_INSN_SIZE)
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static int __initdata_or_module debug_alternative;
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static int __init debug_alt(char *str)
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{
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debug_alternative = 1;
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return 1;
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}
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__setup("debug-alternative", debug_alt);
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#define DPRINTK(fmt, args...) \
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do { \
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if (debug_alternative) \
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printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##args); \
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} while (0)
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#define DUMP_WORDS(buf, count, fmt, args...) \
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do { \
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if (unlikely(debug_alternative)) { \
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int _j; \
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union loongarch_instruction *_buf = buf; \
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\
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if (!(count)) \
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break; \
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\
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printk(KERN_DEBUG fmt, ##args); \
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for (_j = 0; _j < count - 1; _j++) \
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printk(KERN_CONT "<%08x> ", _buf[_j].word); \
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printk(KERN_CONT "<%08x>\n", _buf[_j].word); \
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} \
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} while (0)
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/* Use this to add nops to a buffer, then text_poke the whole buffer. */
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static void __init_or_module add_nops(union loongarch_instruction *insn, int count)
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{
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while (count--) {
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insn->word = INSN_NOP;
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insn++;
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}
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}
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/* Is the jump addr in local .altinstructions */
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static inline bool in_alt_jump(unsigned long jump, void *start, void *end)
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{
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return jump >= (unsigned long)start && jump < (unsigned long)end;
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}
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static void __init_or_module recompute_jump(union loongarch_instruction *buf,
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union loongarch_instruction *dest, union loongarch_instruction *src,
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void *start, void *end)
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{
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unsigned int si, si_l, si_h;
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unsigned long cur_pc, jump_addr, pc;
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long offset;
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cur_pc = (unsigned long)src;
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pc = (unsigned long)dest;
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si_l = src->reg0i26_format.immediate_l;
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si_h = src->reg0i26_format.immediate_h;
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switch (src->reg0i26_format.opcode) {
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case b_op:
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case bl_op:
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jump_addr = cur_pc + sign_extend((si_h << 16 | si_l) << 2, 27);
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if (in_alt_jump(jump_addr, start, end))
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return;
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offset = jump_addr - pc;
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BUG_ON(offset < -SZ_128M || offset >= SZ_128M);
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offset >>= 2;
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buf->reg0i26_format.immediate_h = offset >> 16;
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buf->reg0i26_format.immediate_l = offset;
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return;
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}
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si_l = src->reg1i21_format.immediate_l;
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si_h = src->reg1i21_format.immediate_h;
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switch (src->reg1i21_format.opcode) {
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case bceqz_op: /* bceqz_op = bcnez_op */
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BUG_ON(buf->reg1i21_format.rj & BIT(4));
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fallthrough;
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case beqz_op:
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case bnez_op:
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jump_addr = cur_pc + sign_extend((si_h << 16 | si_l) << 2, 22);
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if (in_alt_jump(jump_addr, start, end))
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return;
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offset = jump_addr - pc;
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BUG_ON(offset < -SZ_4M || offset >= SZ_4M);
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offset >>= 2;
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buf->reg1i21_format.immediate_h = offset >> 16;
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buf->reg1i21_format.immediate_l = offset;
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return;
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}
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si = src->reg2i16_format.immediate;
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switch (src->reg2i16_format.opcode) {
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case beq_op:
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case bne_op:
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case blt_op:
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case bge_op:
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case bltu_op:
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case bgeu_op:
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jump_addr = cur_pc + sign_extend(si << 2, 17);
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if (in_alt_jump(jump_addr, start, end))
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return;
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offset = jump_addr - pc;
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BUG_ON(offset < -SZ_128K || offset >= SZ_128K);
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offset >>= 2;
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buf->reg2i16_format.immediate = offset;
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return;
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}
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}
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static int __init_or_module copy_alt_insns(union loongarch_instruction *buf,
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union loongarch_instruction *dest, union loongarch_instruction *src, int nr)
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{
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int i;
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for (i = 0; i < nr; i++) {
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buf[i].word = src[i].word;
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if (is_pc_ins(&src[i])) {
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pr_err("Not support pcrel instruction at present!");
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return -EINVAL;
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}
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if (is_branch_ins(&src[i]) &&
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src[i].reg2i16_format.opcode != jirl_op) {
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recompute_jump(&buf[i], &dest[i], &src[i], src, src + nr);
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}
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}
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return 0;
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}
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/*
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* text_poke_early - Update instructions on a live kernel at boot time
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*
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* When you use this code to patch more than one byte of an instruction
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* you need to make sure that other CPUs cannot execute this code in parallel.
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* Also no thread must be currently preempted in the middle of these
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* instructions. And on the local CPU you need to be protected again NMI or MCE
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* handlers seeing an inconsistent instruction while you patch.
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*/
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static void *__init_or_module text_poke_early(union loongarch_instruction *insn,
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union loongarch_instruction *buf, unsigned int nr)
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{
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int i;
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unsigned long flags;
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|
||||
local_irq_save(flags);
|
||||
|
||||
for (i = 0; i < nr; i++)
|
||||
insn[i].word = buf[i].word;
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
wbflush();
|
||||
flush_icache_range((unsigned long)insn, (unsigned long)(insn + nr));
|
||||
|
||||
return insn;
|
||||
}
|
||||
|
||||
/*
|
||||
* Replace instructions with better alternatives for this CPU type. This runs
|
||||
* before SMP is initialized to avoid SMP problems with self modifying code.
|
||||
* This implies that asymmetric systems where APs have less capabilities than
|
||||
* the boot processor are not handled. Tough. Make sure you disable such
|
||||
* features by hand.
|
||||
*/
|
||||
void __init_or_module apply_alternatives(struct alt_instr *start, struct alt_instr *end)
|
||||
{
|
||||
struct alt_instr *a;
|
||||
unsigned int nr_instr, nr_repl, nr_insnbuf;
|
||||
union loongarch_instruction *instr, *replacement;
|
||||
union loongarch_instruction insnbuf[MAX_PATCH_SIZE];
|
||||
|
||||
DPRINTK("alt table %px, -> %px", start, end);
|
||||
/*
|
||||
* The scan order should be from start to end. A later scanned
|
||||
* alternative code can overwrite previously scanned alternative code.
|
||||
* Some kernel functions (e.g. memcpy, memset, etc) use this order to
|
||||
* patch code.
|
||||
*
|
||||
* So be careful if you want to change the scan order to any other
|
||||
* order.
|
||||
*/
|
||||
for (a = start; a < end; a++) {
|
||||
nr_insnbuf = 0;
|
||||
|
||||
instr = (void *)&a->instr_offset + a->instr_offset;
|
||||
replacement = (void *)&a->replace_offset + a->replace_offset;
|
||||
|
||||
BUG_ON(a->instrlen > sizeof(insnbuf));
|
||||
BUG_ON(a->instrlen & 0x3);
|
||||
BUG_ON(a->replacementlen & 0x3);
|
||||
|
||||
nr_instr = a->instrlen / LOONGARCH_INSN_SIZE;
|
||||
nr_repl = a->replacementlen / LOONGARCH_INSN_SIZE;
|
||||
|
||||
if (!cpu_has(a->feature)) {
|
||||
DPRINTK("feat not exist: %d, old: (%px len: %d), repl: (%px, len: %d)",
|
||||
a->feature, instr, a->instrlen,
|
||||
replacement, a->replacementlen);
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
DPRINTK("feat: %d, old: (%px len: %d), repl: (%px, len: %d)",
|
||||
a->feature, instr, a->instrlen,
|
||||
replacement, a->replacementlen);
|
||||
|
||||
DUMP_WORDS(instr, nr_instr, "%px: old_insn: ", instr);
|
||||
DUMP_WORDS(replacement, nr_repl, "%px: rpl_insn: ", replacement);
|
||||
|
||||
copy_alt_insns(insnbuf, instr, replacement, nr_repl);
|
||||
nr_insnbuf = nr_repl;
|
||||
|
||||
if (nr_instr > nr_repl) {
|
||||
add_nops(insnbuf + nr_repl, nr_instr - nr_repl);
|
||||
nr_insnbuf += nr_instr - nr_repl;
|
||||
}
|
||||
DUMP_WORDS(insnbuf, nr_insnbuf, "%px: final_insn: ", instr);
|
||||
|
||||
text_poke_early(instr, insnbuf, nr_insnbuf);
|
||||
}
|
||||
}
|
||||
|
||||
void __init alternative_instructions(void)
|
||||
{
|
||||
apply_alternatives(__alt_instructions, __alt_instructions_end);
|
||||
|
||||
alternatives_patched = 1;
|
||||
}
|
||||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/fs.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/alternative.h>
|
||||
|
||||
static int rela_stack_push(s64 stack_value, s64 *rela_stack, size_t *rela_stack_top)
|
||||
{
|
||||
|
|
@ -456,3 +457,17 @@ void *module_alloc(unsigned long size)
|
|||
return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
|
||||
GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, __builtin_return_address(0));
|
||||
}
|
||||
|
||||
int module_finalize(const Elf_Ehdr *hdr,
|
||||
const Elf_Shdr *sechdrs, struct module *mod)
|
||||
{
|
||||
const Elf_Shdr *s, *se;
|
||||
const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
|
||||
|
||||
for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
|
||||
if (!strcmp(".altinstructions", secstrs + s->sh_name))
|
||||
apply_alternatives((void *)s->sh_addr, (void *)s->sh_addr + s->sh_size);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,7 +31,9 @@
|
|||
#include <linux/swiotlb.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/alternative.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/bugs.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/dma.h>
|
||||
|
|
@ -80,6 +82,11 @@ const char *get_system_type(void)
|
|||
return "generic-loongson-machine";
|
||||
}
|
||||
|
||||
void __init check_bugs(void)
|
||||
{
|
||||
alternative_instructions();
|
||||
}
|
||||
|
||||
static const char *dmi_string_parse(const struct dmi_header *dm, u8 s)
|
||||
{
|
||||
const u8 *bp = ((u8 *) dm) + dm->length;
|
||||
|
|
|
|||
|
|
@ -54,6 +54,18 @@ SECTIONS
|
|||
. = ALIGN(PECOFF_SEGMENT_ALIGN);
|
||||
_etext = .;
|
||||
|
||||
/*
|
||||
* struct alt_inst entries. From the header (alternative.h):
|
||||
* "Alternative instructions for different CPU types or capabilities"
|
||||
* Think locking instructions on spinlocks.
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
.altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) {
|
||||
__alt_instructions = .;
|
||||
*(.altinstructions)
|
||||
__alt_instructions_end = .;
|
||||
}
|
||||
|
||||
.got : ALIGN(16) { *(.got) }
|
||||
.plt : ALIGN(16) { *(.plt) }
|
||||
.got.plt : ALIGN(16) { *(.got.plt) }
|
||||
|
|
|
|||
Loading…
Reference in New Issue