PRM reset control dts changes for v5.5 merge window
This series of changes adds the PRM reset driver nodes for am3/4, omap4/5 and dra7 SoCs. The reset driver changes make it easier to add support for various accelerators for TI SoCs in a more generic way. Note that this branch is based on the PRM reset driver changes branch. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl28UrgRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXPQvw/+Kz/OaUWXc6NCGqbgrjvQZbJMzWykeuP3 QyIzQ/k6x9B1VqkHvnmbAUKEpROXe7/t8QaVZs2WfQLb/3QvOJtEN5KlgGOC1ofF VLWR1aSU1bApDIbTf0tIhIEkmsm/qJvm4QlRBLahQEtP/2LRuZMybikBgbEteFMB zgMUPjqc//gGI1Y8H90ntWlCA0runosrxJ83qJ4O74RMzBiH30h3qZFq7Xt4O/az x0B4u+RBB3hnetq6oHBsk6TFbE0qmOBYSx81w40GM4Rn5Xgvq62PaoRHez/qLRRB 3GhtfIUb5bJX3w8wQF6wyIUQfIFjYKDut3mldx1zR01x8QwYMl5b8aD9M5MIern4 +KVT5rtjllnbMQYhOmQKky5UCKU1SOvYZDfN//4S68YF0DZ257vYFkeXIWHYA+pr Cc8lVAgCqDV5WlBBXy2F6uZC7vQCdpPFI2ljEPryiEumJ3FlK+nY7WmpusJ6grau BiJakyYS0dqqoJS+LH7GtB3PLChgGXIQd9SWF5NvCzbtr+4ve7dUCzTs/UitUpET 9B3kaoHE9s9UvozZkHFPxIhR7o2uAfSqUUMNCWplXy5jhPl6RFPB0myV66ai8v3U ZVO+EAF0Bx47zz0riBlqraiMBybohohZAijZjQztHyeKE2CfBc1ErUPFAur32bF6 ML9ze/G+SkI= =4DAS -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt PRM reset control dts changes for v5.5 merge window This series of changes adds the PRM reset driver nodes for am3/4, omap4/5 and dra7 SoCs. The reset driver changes make it easier to add support for various accelerators for TI SoCs in a more generic way. Note that this branch is based on the PRM reset driver changes branch. * tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: omap5: Add PRM data ARM: dts: am43xx: Add PRM data ARM: dts: am33xx: Add PRM data ARM: dts: omap4: add PRM nodes ARM: dts: dra7: add PRM nodes soc: ti: omap-prm: add omap5 PRM data soc: ti: omap-prm: add am4 PRM data soc: ti: omap-prm: add dra7 PRM data soc: ti: omap-prm: add data for am33xx soc: ti: omap-prm: add omap4 PRM data soc: ti: omap-prm: add support for denying idle for reset clockdomain soc: ti: omap-prm: poll for reset complete during de-assert soc: ti: add initial PRM driver with reset control support dt-bindings: omap: add new binding for PRM instances Link: https://lore.kernel.org/r/pull-1572623173-281197@atomide.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
19e489aa9b
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@ -0,0 +1,29 @@
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OMAP PRM instance bindings
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Power and Reset Manager is an IP block on OMAP family of devices which
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handle the power domains and their current state, and provide reset
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handling for the domains and/or separate IP blocks under the power domain
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hierarchy.
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Required properties:
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- compatible: Must contain one of the following:
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"ti,am3-prm-inst"
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"ti,am4-prm-inst"
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"ti,omap4-prm-inst"
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"ti,omap5-prm-inst"
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"ti,dra7-prm-inst"
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and additionally must contain:
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"ti,omap-prm-inst"
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- reg: Contains PRM instance register address range
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(base address and length)
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Optional properties:
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- #reset-cells: Should be 1 if the PRM instance in question supports resets.
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Example:
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prm_dsp2: prm@1b00 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1b00 0x40>;
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#reset-cells = <1>;
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};
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@ -462,3 +462,29 @@
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#include "am33xx-l4.dtsi"
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#include "am33xx-clocks.dtsi"
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&prcm {
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prm_per: prm@c00 {
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compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
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reg = <0xc00 0x100>;
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#reset-cells = <1>;
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};
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prm_wkup: prm@d00 {
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compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
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reg = <0xd00 0x100>;
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#reset-cells = <1>;
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};
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prm_device: prm@f00 {
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compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
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reg = <0xf00 0x100>;
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#reset-cells = <1>;
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};
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prm_gfx: prm@1100 {
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compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
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reg = <0x1100 0x100>;
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#reset-cells = <1>;
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};
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};
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@ -374,3 +374,29 @@
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#include "am437x-l4.dtsi"
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#include "am43xx-clocks.dtsi"
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&prcm {
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prm_gfx: prm@400 {
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compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
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reg = <0x400 0x100>;
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#reset-cells = <1>;
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};
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prm_per: prm@800 {
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compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
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reg = <0x800 0x100>;
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#reset-cells = <1>;
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};
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prm_wkup: prm@2000 {
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compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
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reg = <0x2000 0x100>;
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#reset-cells = <1>;
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};
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prm_device: prm@4000 {
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compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
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reg = <0x4000 0x100>;
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#reset-cells = <1>;
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};
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};
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@ -763,3 +763,54 @@
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#include "dra7-l4.dtsi"
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#include "dra7xx-clocks.dtsi"
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&prm {
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prm_dsp1: prm@400 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x400 0x100>;
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#reset-cells = <1>;
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};
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prm_ipu: prm@500 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x500 0x100>;
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#reset-cells = <1>;
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};
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prm_core: prm@700 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x700 0x100>;
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#reset-cells = <1>;
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};
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prm_iva: prm@f00 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0xf00 0x100>;
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};
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prm_dsp2: prm@1b00 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1b00 0x40>;
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#reset-cells = <1>;
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};
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prm_eve1: prm@1b40 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1b40 0x40>;
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};
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prm_eve2: prm@1b80 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1b80 0x40>;
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};
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prm_eve3: prm@1bc0 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1bc0 0x40>;
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};
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prm_eve4: prm@1c00 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1c00 0x60>;
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};
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};
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@ -1005,7 +1005,7 @@
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ranges = <0x0 0x6000 0x2000>;
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prm: prm@0 {
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compatible = "ti,omap4-prm";
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compatible = "ti,omap4-prm", "simple-bus";
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reg = <0x0 0x2000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -442,3 +442,29 @@
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#include "omap4-l4.dtsi"
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#include "omap4-l4-abe.dtsi"
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#include "omap44xx-clocks.dtsi"
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&prm {
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prm_tesla: prm@400 {
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compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
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reg = <0x400 0x100>;
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#reset-cells = <1>;
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};
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prm_core: prm@700 {
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compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
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reg = <0x700 0x100>;
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#reset-cells = <1>;
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};
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prm_ivahd: prm@f00 {
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compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
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reg = <0xf00 0x100>;
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#reset-cells = <1>;
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};
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prm_device: prm@1b00 {
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compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
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reg = <0x1b00 0x40>;
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#reset-cells = <1>;
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};
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};
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@ -435,3 +435,29 @@
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#include "omap5-l4-abe.dtsi"
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#include "omap54xx-clocks.dtsi"
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&prm {
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prm_dsp: prm@400 {
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compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
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reg = <0x400 0x100>;
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#reset-cells = <1>;
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};
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prm_core: prm@700 {
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compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
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reg = <0x700 0x100>;
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#reset-cells = <1>;
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};
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prm_iva: prm@1200 {
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compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
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reg = <0x1200 0x100>;
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#reset-cells = <1>;
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};
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prm_device: prm@1c00 {
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compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
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reg = <0x1c00 0x100>;
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#reset-cells = <1>;
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};
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};
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@ -109,6 +109,7 @@ config ARCH_OMAP2PLUS
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select TI_SYSC
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select OMAP_IRQCHIP
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select CLKSRC_TI_32K
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select ARCH_HAS_RESET_CONTROLLER
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help
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Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
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@ -6,6 +6,7 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_QMSS) += knav_qmss.o
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knav_qmss-y := knav_qmss_queue.o knav_qmss_acc.o
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obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA) += knav_dma.o
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obj-$(CONFIG_AMX3_PM) += pm33xx.o
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obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_prm.o
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obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o
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obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o
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obj-$(CONFIG_TI_SCI_INTA_MSI_DOMAIN) += ti_sci_inta_msi.o
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@ -0,0 +1,391 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* OMAP2+ PRM driver
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*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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* Tero Kristo <t-kristo@ti.com>
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*/
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/delay.h>
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#include <linux/platform_data/ti-prm.h>
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struct omap_rst_map {
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s8 rst;
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s8 st;
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};
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struct omap_prm_data {
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u32 base;
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const char *name;
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const char *clkdm_name;
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u16 rstctrl;
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u16 rstst;
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const struct omap_rst_map *rstmap;
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u8 flags;
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};
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struct omap_prm {
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const struct omap_prm_data *data;
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void __iomem *base;
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};
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struct omap_reset_data {
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struct reset_controller_dev rcdev;
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struct omap_prm *prm;
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u32 mask;
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spinlock_t lock;
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struct clockdomain *clkdm;
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struct device *dev;
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};
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#define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev)
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#define OMAP_MAX_RESETS 8
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#define OMAP_RESET_MAX_WAIT 10000
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#define OMAP_PRM_HAS_RSTCTRL BIT(0)
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#define OMAP_PRM_HAS_RSTST BIT(1)
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#define OMAP_PRM_HAS_NO_CLKDM BIT(2)
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#define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST)
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static const struct omap_rst_map rst_map_0[] = {
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{ .rst = 0, .st = 0 },
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{ .rst = -1 },
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};
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static const struct omap_rst_map rst_map_01[] = {
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{ .rst = 0, .st = 0 },
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{ .rst = 1, .st = 1 },
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{ .rst = -1 },
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};
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static const struct omap_rst_map rst_map_012[] = {
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{ .rst = 0, .st = 0 },
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{ .rst = 1, .st = 1 },
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{ .rst = 2, .st = 2 },
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{ .rst = -1 },
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};
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static const struct omap_prm_data omap4_prm_data[] = {
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{ .name = "tesla", .base = 0x4a306400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
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{ .name = "core", .base = 0x4a306700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati", .rstmap = rst_map_012 },
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{ .name = "ivahd", .base = 0x4a306f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
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{ .name = "device", .base = 0x4a307b00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
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{ },
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};
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static const struct omap_prm_data omap5_prm_data[] = {
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{ .name = "dsp", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
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{ .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu", .rstmap = rst_map_012 },
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{ .name = "iva", .base = 0x4ae07200, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
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{ .name = "device", .base = 0x4ae07c00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
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{ },
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};
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static const struct omap_prm_data dra7_prm_data[] = {
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{ .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
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{ .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 },
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{ .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu2", .rstmap = rst_map_012 },
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{ .name = "iva", .base = 0x4ae06f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
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{ .name = "dsp2", .base = 0x4ae07b00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
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{ .name = "eve1", .base = 0x4ae07b40, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
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{ .name = "eve2", .base = 0x4ae07b80, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
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{ .name = "eve3", .base = 0x4ae07bc0, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
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{ .name = "eve4", .base = 0x4ae07c00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
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{ },
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};
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static const struct omap_rst_map am3_per_rst_map[] = {
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{ .rst = 1 },
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{ .rst = -1 },
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};
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static const struct omap_rst_map am3_wkup_rst_map[] = {
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{ .rst = 3, .st = 5 },
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{ .rst = -1 },
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};
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static const struct omap_prm_data am3_prm_data[] = {
|
||||
{ .name = "per", .base = 0x44e00c00, .rstctrl = 0x0, .rstmap = am3_per_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL, .clkdm_name = "pruss_ocp" },
|
||||
{ .name = "wkup", .base = 0x44e00d00, .rstctrl = 0x0, .rstst = 0xc, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
|
||||
{ .name = "device", .base = 0x44e00f00, .rstctrl = 0x0, .rstst = 0x8, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
|
||||
{ .name = "gfx", .base = 0x44e01100, .rstctrl = 0x4, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3" },
|
||||
{ },
|
||||
};
|
||||
|
||||
static const struct omap_rst_map am4_per_rst_map[] = {
|
||||
{ .rst = 1, .st = 0 },
|
||||
{ .rst = -1 },
|
||||
};
|
||||
|
||||
static const struct omap_rst_map am4_device_rst_map[] = {
|
||||
{ .rst = 0, .st = 1 },
|
||||
{ .rst = 1, .st = 0 },
|
||||
{ .rst = -1 },
|
||||
};
|
||||
|
||||
static const struct omap_prm_data am4_prm_data[] = {
|
||||
{ .name = "gfx", .base = 0x44df0400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3" },
|
||||
{ .name = "per", .base = 0x44df0800, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map, .clkdm_name = "pruss_ocp" },
|
||||
{ .name = "wkup", .base = 0x44df2000, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_NO_CLKDM },
|
||||
{ .name = "device", .base = 0x44df4000, .rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
|
||||
{ },
|
||||
};
|
||||
|
||||
static const struct of_device_id omap_prm_id_table[] = {
|
||||
{ .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data },
|
||||
{ .compatible = "ti,omap5-prm-inst", .data = omap5_prm_data },
|
||||
{ .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data },
|
||||
{ .compatible = "ti,am3-prm-inst", .data = am3_prm_data },
|
||||
{ .compatible = "ti,am4-prm-inst", .data = am4_prm_data },
|
||||
{ },
|
||||
};
|
||||
|
||||
static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id)
|
||||
{
|
||||
if (reset->mask & BIT(id))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int omap_reset_get_st_bit(struct omap_reset_data *reset,
|
||||
unsigned long id)
|
||||
{
|
||||
const struct omap_rst_map *map = reset->prm->data->rstmap;
|
||||
|
||||
while (map->rst >= 0) {
|
||||
if (map->rst == id)
|
||||
return map->st;
|
||||
|
||||
map++;
|
||||
}
|
||||
|
||||
return id;
|
||||
}
|
||||
|
||||
static int omap_reset_status(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct omap_reset_data *reset = to_omap_reset_data(rcdev);
|
||||
u32 v;
|
||||
int st_bit = omap_reset_get_st_bit(reset, id);
|
||||
bool has_rstst = reset->prm->data->rstst ||
|
||||
(reset->prm->data->flags & OMAP_PRM_HAS_RSTST);
|
||||
|
||||
/* Check if we have rstst */
|
||||
if (!has_rstst)
|
||||
return -ENOTSUPP;
|
||||
|
||||
/* Check if hw reset line is asserted */
|
||||
v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
|
||||
if (v & BIT(id))
|
||||
return 1;
|
||||
|
||||
/*
|
||||
* Check reset status, high value means reset sequence has been
|
||||
* completed successfully so we can return 0 here (reset deasserted)
|
||||
*/
|
||||
v = readl_relaxed(reset->prm->base + reset->prm->data->rstst);
|
||||
v >>= st_bit;
|
||||
v &= 1;
|
||||
|
||||
return !v;
|
||||
}
|
||||
|
||||
static int omap_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct omap_reset_data *reset = to_omap_reset_data(rcdev);
|
||||
u32 v;
|
||||
unsigned long flags;
|
||||
|
||||
/* assert the reset control line */
|
||||
spin_lock_irqsave(&reset->lock, flags);
|
||||
v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
|
||||
v |= 1 << id;
|
||||
writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl);
|
||||
spin_unlock_irqrestore(&reset->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct omap_reset_data *reset = to_omap_reset_data(rcdev);
|
||||
u32 v;
|
||||
int st_bit;
|
||||
bool has_rstst;
|
||||
unsigned long flags;
|
||||
struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev);
|
||||
int ret = 0;
|
||||
|
||||
has_rstst = reset->prm->data->rstst ||
|
||||
(reset->prm->data->flags & OMAP_PRM_HAS_RSTST);
|
||||
|
||||
if (has_rstst) {
|
||||
st_bit = omap_reset_get_st_bit(reset, id);
|
||||
|
||||
/* Clear the reset status by writing 1 to the status bit */
|
||||
v = 1 << st_bit;
|
||||
writel_relaxed(v, reset->prm->base + reset->prm->data->rstst);
|
||||
}
|
||||
|
||||
if (reset->clkdm)
|
||||
pdata->clkdm_deny_idle(reset->clkdm);
|
||||
|
||||
/* de-assert the reset control line */
|
||||
spin_lock_irqsave(&reset->lock, flags);
|
||||
v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
|
||||
v &= ~(1 << id);
|
||||
writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl);
|
||||
spin_unlock_irqrestore(&reset->lock, flags);
|
||||
|
||||
if (!has_rstst)
|
||||
goto exit;
|
||||
|
||||
/* wait for the status to be set */
|
||||
ret = readl_relaxed_poll_timeout(reset->prm->base +
|
||||
reset->prm->data->rstst,
|
||||
v, v & BIT(st_bit), 1,
|
||||
OMAP_RESET_MAX_WAIT);
|
||||
if (ret)
|
||||
pr_err("%s: timedout waiting for %s:%lu\n", __func__,
|
||||
reset->prm->data->name, id);
|
||||
|
||||
exit:
|
||||
if (reset->clkdm)
|
||||
pdata->clkdm_allow_idle(reset->clkdm);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct reset_control_ops omap_reset_ops = {
|
||||
.assert = omap_reset_assert,
|
||||
.deassert = omap_reset_deassert,
|
||||
.status = omap_reset_status,
|
||||
};
|
||||
|
||||
static int omap_prm_reset_xlate(struct reset_controller_dev *rcdev,
|
||||
const struct of_phandle_args *reset_spec)
|
||||
{
|
||||
struct omap_reset_data *reset = to_omap_reset_data(rcdev);
|
||||
|
||||
if (!_is_valid_reset(reset, reset_spec->args[0]))
|
||||
return -EINVAL;
|
||||
|
||||
return reset_spec->args[0];
|
||||
}
|
||||
|
||||
static int omap_prm_reset_init(struct platform_device *pdev,
|
||||
struct omap_prm *prm)
|
||||
{
|
||||
struct omap_reset_data *reset;
|
||||
const struct omap_rst_map *map;
|
||||
struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
||||
char buf[32];
|
||||
|
||||
/*
|
||||
* Check if we have controllable resets. If either rstctrl is non-zero
|
||||
* or OMAP_PRM_HAS_RSTCTRL flag is set, we have reset control register
|
||||
* for the domain.
|
||||
*/
|
||||
if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL))
|
||||
return 0;
|
||||
|
||||
/* Check if we have the pdata callbacks in place */
|
||||
if (!pdata || !pdata->clkdm_lookup || !pdata->clkdm_deny_idle ||
|
||||
!pdata->clkdm_allow_idle)
|
||||
return -EINVAL;
|
||||
|
||||
map = prm->data->rstmap;
|
||||
if (!map)
|
||||
return -EINVAL;
|
||||
|
||||
reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
|
||||
if (!reset)
|
||||
return -ENOMEM;
|
||||
|
||||
reset->rcdev.owner = THIS_MODULE;
|
||||
reset->rcdev.ops = &omap_reset_ops;
|
||||
reset->rcdev.of_node = pdev->dev.of_node;
|
||||
reset->rcdev.nr_resets = OMAP_MAX_RESETS;
|
||||
reset->rcdev.of_xlate = omap_prm_reset_xlate;
|
||||
reset->rcdev.of_reset_n_cells = 1;
|
||||
reset->dev = &pdev->dev;
|
||||
spin_lock_init(&reset->lock);
|
||||
|
||||
reset->prm = prm;
|
||||
|
||||
sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name :
|
||||
prm->data->name);
|
||||
|
||||
if (!(prm->data->flags & OMAP_PRM_HAS_NO_CLKDM)) {
|
||||
reset->clkdm = pdata->clkdm_lookup(buf);
|
||||
if (!reset->clkdm)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
while (map->rst >= 0) {
|
||||
reset->mask |= BIT(map->rst);
|
||||
map++;
|
||||
}
|
||||
|
||||
return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
|
||||
}
|
||||
|
||||
static int omap_prm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
const struct omap_prm_data *data;
|
||||
struct omap_prm *prm;
|
||||
const struct of_device_id *match;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
|
||||
match = of_match_device(omap_prm_id_table, &pdev->dev);
|
||||
if (!match)
|
||||
return -ENOTSUPP;
|
||||
|
||||
prm = devm_kzalloc(&pdev->dev, sizeof(*prm), GFP_KERNEL);
|
||||
if (!prm)
|
||||
return -ENOMEM;
|
||||
|
||||
data = match->data;
|
||||
|
||||
while (data->base != res->start) {
|
||||
if (!data->base)
|
||||
return -EINVAL;
|
||||
data++;
|
||||
}
|
||||
|
||||
prm->data = data;
|
||||
|
||||
prm->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (!prm->base)
|
||||
return -ENOMEM;
|
||||
|
||||
return omap_prm_reset_init(pdev, prm);
|
||||
}
|
||||
|
||||
static struct platform_driver omap_prm_driver = {
|
||||
.probe = omap_prm_probe,
|
||||
.driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.of_match_table = omap_prm_id_table,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(omap_prm_driver);
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* TI PRM (Power & Reset Manager) platform data
|
||||
*
|
||||
* Copyright (C) 2019 Texas Instruments, Inc.
|
||||
*
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_PLATFORM_DATA_TI_PRM_H
|
||||
#define _LINUX_PLATFORM_DATA_TI_PRM_H
|
||||
|
||||
struct clockdomain;
|
||||
|
||||
struct ti_prm_platform_data {
|
||||
void (*clkdm_deny_idle)(struct clockdomain *clkdm);
|
||||
void (*clkdm_allow_idle)(struct clockdomain *clkdm);
|
||||
struct clockdomain * (*clkdm_lookup)(const char *name);
|
||||
};
|
||||
|
||||
#endif /* _LINUX_PLATFORM_DATA_TI_PRM_H */
|
||||
Loading…
Reference in New Issue