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pinctrl: renesas: Updates for v6.3 

- Add pin groups for Video-In channels 4 and 5 on R-Car H3 ES1.x,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v6.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v6.3

  - Add pin groups for Video-In channels 4 and 5 on R-Car H3 ES1.x,
  - Miscellaneous fixes and improvements.
This commit is contained in:
Linus Walleij 2023-01-30 23:12:12 +01:00
parent 9da134e270 698485cd87
commit 19a2c394a2
3 changed files with 317 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

244
drivers/pinctrl/renesas/pfc-r8a77950.c
View File

@ -3820,6 +3820,186 @@ static const unsigned int usb31_mux[] = {
USB31_PWEN_MARK, USB31_OVC_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const unsigned int vin4_data18_a_pins[] = {
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_a_mux[] = {
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data18_b_pins[] = {
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data_a_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data_a_mux[] = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data_b_pins[] = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data_b_mux[] = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
};
static const unsigned int vin4_sync_mux[] = {
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
};
static const unsigned int vin4_field_pins[] = {
/* FIELD */
RCAR_GP_PIN(1, 16),
};
static const unsigned int vin4_field_mux[] = {
VI4_FIELD_MARK,
};
static const unsigned int vin4_clkenb_pins[] = {
/* CLKENB */
RCAR_GP_PIN(1, 19),
};
static const unsigned int vin4_clkenb_mux[] = {
VI4_CLKENB_MARK,
};
static const unsigned int vin4_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 27),
};
static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
/* - VIN5 ------------------------------------------------------------------- */
static const unsigned int vin5_data_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin5_data_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
};
static const unsigned int vin5_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
};
static const unsigned int vin5_sync_mux[] = {
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
};
static const unsigned int vin5_field_pins[] = {
RCAR_GP_PIN(1, 11),
};
static const unsigned int vin5_field_mux[] = {
/* FIELD */
VI5_FIELD_MARK,
};
static const unsigned int vin5_clkenb_pins[] = {
RCAR_GP_PIN(1, 20),
};
static const unsigned int vin5_clkenb_mux[] = {
/* CLKENB */
VI5_CLKENB_MARK,
};
static const unsigned int vin5_clk_pins[] = {
RCAR_GP_PIN(1, 21),
};
static const unsigned int vin5_clk_mux[] = {
/* CLK */
VI5_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
@ -4141,6 +4321,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(usb2),
SH_PFC_PIN_GROUP(usb30),
SH_PFC_PIN_GROUP(usb31),
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
BUS_DATA_PIN_GROUP(vin5_data, 8),
BUS_DATA_PIN_GROUP(vin5_data, 10),
BUS_DATA_PIN_GROUP(vin5_data, 12),
BUS_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
};
static const char * const audio_clk_groups[] = {
@ -4637,6 +4845,40 @@ static const char * const usb31_groups[] = {
"usb31",
};
static const char * const vin4_groups[] = {
"vin4_data8_a",
"vin4_data10_a",
"vin4_data12_a",
"vin4_data16_a",
"vin4_data18_a",
"vin4_data20_a",
"vin4_data24_a",
"vin4_data8_b",
"vin4_data10_b",
"vin4_data12_b",
"vin4_data16_b",
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
"vin4_g8",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
"vin4_clk",
};
static const char * const vin5_groups[] = {
"vin5_data8",
"vin5_data10",
"vin5_data12",
"vin5_data16",
"vin5_high8",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
"vin5_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
@ -4696,6 +4938,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(usb2),
SH_PFC_FUNCTION(usb30),
SH_PFC_FUNCTION(usb31),
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

112
drivers/pinctrl/renesas/pfc-r8a779g0.c
View File

@ -206,66 +206,66 @@
#define GPSR5_0 FM(AVB2_AVTP_PPS)
/* GPSR 6 */
#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
/* GPSR7 */
#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
/* GPSR8 */
#define GPSR8_13 F_(GP8_13, IP1SR8_23_20)
#define GPSR8_12 F_(GP8_12, IP1SR8_19_16)
#define GPSR8_11 F_(SDA5, IP1SR8_15_12)
#define GPSR8_10 F_(SCL5, IP1SR8_11_8)
#define GPSR8_9 F_(SDA4, IP1SR8_7_4)
#define GPSR8_8 F_(SCL4, IP1SR8_3_0)
#define GPSR8_7 F_(SDA3, IP0SR8_31_28)
#define GPSR8_6 F_(SCL3, IP0SR8_27_24)
#define GPSR8_5 F_(SDA2, IP0SR8_23_20)
#define GPSR8_4 F_(SCL2, IP0SR8_19_16)
#define GPSR8_3 F_(SDA1, IP0SR8_15_12)
#define GPSR8_2 F_(SCL1, IP0SR8_11_8)
#define GPSR8_1 F_(SDA0, IP0SR8_7_4)
#define GPSR8_0 F_(SCL0, IP0SR8_3_0)
#define GPSR8_13 F_(GP8_13, IP1SR8_23_20)
#define GPSR8_12 F_(GP8_12, IP1SR8_19_16)
#define GPSR8_11 F_(SDA5, IP1SR8_15_12)
#define GPSR8_10 F_(SCL5, IP1SR8_11_8)
#define GPSR8_9 F_(SDA4, IP1SR8_7_4)
#define GPSR8_8 F_(SCL4, IP1SR8_3_0)
#define GPSR8_7 F_(SDA3, IP0SR8_31_28)
#define GPSR8_6 F_(SCL3, IP0SR8_27_24)
#define GPSR8_5 F_(SDA2, IP0SR8_23_20)
#define GPSR8_4 F_(SCL2, IP0SR8_19_16)
#define GPSR8_3 F_(SDA1, IP0SR8_15_12)
#define GPSR8_2 F_(SCL1, IP0SR8_11_8)
#define GPSR8_1 F_(SDA0, IP0SR8_7_4)
#define GPSR8_0 F_(SCL0, IP0SR8_3_0)
/* SR0 */
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */

25
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View File

@ -130,6 +130,7 @@ struct rzg2l_dedicated_configs {
struct rzg2l_pinctrl_data {
const char * const *port_pins;
const u32 *port_pin_configs;
unsigned int n_ports;
struct rzg2l_dedicated_configs *dedicated_pins;
unsigned int n_port_pins;
unsigned int n_dedicated_pins;
@ -1124,7 +1125,7 @@ static struct {
}
};
static int rzg2l_gpio_get_gpioint(unsigned int virq)
static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
{
unsigned int gpioint;
unsigned int i;
@ -1133,13 +1134,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq)
port = virq / 8;
bit = virq % 8;
if (port >= ARRAY_SIZE(rzg2l_gpio_configs) ||
bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
if (port >= data->n_ports ||
bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port]))
return -EINVAL;
gpioint = bit;
for (i = 0; i < port; i++)
gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]);
gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]);
return gpioint;
}
@ -1239,7 +1240,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
unsigned long flags;
int gpioint, irq;
gpioint = rzg2l_gpio_get_gpioint(child);
gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data);
if (gpioint < 0)
return gpioint;
@ -1313,8 +1314,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
port = offset / 8;
bit = offset % 8;
if (port >= ARRAY_SIZE(rzg2l_gpio_configs) ||
bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
if (port >= pctrl->data->n_ports ||
bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))
clear_bit(offset, valid_mask);
}
}
@ -1467,6 +1468,12 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
struct rzg2l_pinctrl *pctrl;
int ret;
BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT >
ARRAY_SIZE(rzg2l_gpio_names));
BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
ARRAY_SIZE(rzg2l_gpio_names));
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
@ -1519,6 +1526,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs,
.n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
@ -1527,8 +1535,9 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = rzg2l_gpio_configs,
.n_ports = ARRAY_SIZE(rzg2l_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
.n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
};