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Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm 

* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: footbridge: fix clock event support
  ARM: footbridge: fix debug macros
  ARM: initrd: disable initrds outside of memory
  ARM: extend Code: line by one 16-bit quantity for Thumb instructions
  ARM: 6955/1: cmpxchg syscall should data abort if page not write
  ARM: 6954/1: zImage: fix Thumb2 breakage
  ARM: 6953/1: DT: don't try to access physical address zero
  ARM: 6949/2: mach-u300: fix compilaton warning in IO accessors
  Revert "ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks"
  Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID"
  davinci: make PCM platform devices static
  arm: davinci: Fix fallout from generic irq chip conversion
  ARM: 6894/1: mmci: trigger card detect IRQs on falling and rising edges
  ARM: 6952/1: fix lockdep warning of "unannotated irqs-off"
  ARM: 6951/1: include .bss in memory layout information
  ARM: 6948/1: Fix .size directives for __arm{7,9}tdmi_proc_info
  ARM: 6947/2: mach-u300: fix compilation error in timer
  ARM: 6946/1: vexpress: move v2m clock init to init_early
  ARM: mx51/sdma: Check the chip revision in run-time
  arm: mxs: include asm/processor.h for cpu_relax()
This commit is contained in:
Linus Torvalds 2011-06-15 22:01:36 -07:00
parent 13fca640bb 7d7975a0e1
commit 19a1166fa2
22 changed files with 86 additions and 57 deletions
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6
arch/arm/boot/compressed/head.S
View File

@ -691,9 +691,9 @@ proc_types:
.word 0x41069260 @ ARM926EJ-S (v5TEJ) .word 0x41069260 @ ARM926EJ-S (v5TEJ)
.word 0xff0ffff0 .word 0xff0ffff0
b __arm926ejs_mmu_cache_on W(b) __arm926ejs_mmu_cache_on
b __armv4_mmu_cache_off W(b) __armv4_mmu_cache_off
b __armv5tej_mmu_cache_flush W(b) __armv5tej_mmu_cache_flush
.word 0x00007000 @ ARM7 IDs .word 0x00007000 @ ARM7 IDs
.word 0x0000f000 .word 0x0000f000

3
arch/arm/kernel/devtree.c
View File

@ -76,6 +76,9 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys)
unsigned long dt_root; unsigned long dt_root;
const char *model; const char *model;
if (!dt_phys)
return NULL;
devtree = phys_to_virt(dt_phys); devtree = phys_to_virt(dt_phys);
/* check device tree validity */ /* check device tree validity */

6
arch/arm/kernel/entry-armv.S
View File

@ -435,6 +435,10 @@ __irq_usr:
usr_entry usr_entry
kuser_cmpxchg_check kuser_cmpxchg_check
#ifdef CONFIG_IRQSOFF_TRACER
bl trace_hardirqs_off
#endif
get_thread_info tsk get_thread_info tsk
#ifdef CONFIG_PREEMPT #ifdef CONFIG_PREEMPT
ldr r8, [tsk, #TI_PREEMPT] @ get preempt count ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
@ -453,7 +457,7 @@ __irq_usr:
#endif #endif
mov why, #0 mov why, #0
b ret_to_user b ret_to_user_from_irq
UNWIND(.fnend ) UNWIND(.fnend )
ENDPROC(__irq_usr) ENDPROC(__irq_usr)

2
arch/arm/kernel/entry-common.S
View File

@ -64,6 +64,7 @@ work_resched:
ENTRY(ret_to_user) ENTRY(ret_to_user)
ret_slow_syscall: ret_slow_syscall:
disable_irq @ disable interrupts disable_irq @ disable interrupts
ENTRY(ret_to_user_from_irq)
ldr r1, [tsk, #TI_FLAGS] ldr r1, [tsk, #TI_FLAGS]
tst r1, #_TIF_WORK_MASK tst r1, #_TIF_WORK_MASK
bne work_pending bne work_pending
@ -75,6 +76,7 @@ no_work_pending:
arch_ret_to_user r1, lr arch_ret_to_user r1, lr
restore_user_regs fast = 0, offset = 0 restore_user_regs fast = 0, offset = 0
ENDPROC(ret_to_user_from_irq)
ENDPROC(ret_to_user) ENDPROC(ret_to_user)
/* /*

4
arch/arm/kernel/traps.c
View File

@ -139,7 +139,7 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
fs = get_fs(); fs = get_fs();
set_fs(KERNEL_DS); set_fs(KERNEL_DS);
for (i = -4; i < 1; i++) { for (i = -4; i < 1 + !!thumb; i++) {
unsigned int val, bad; unsigned int val, bad;
if (thumb) if (thumb)
@ -563,7 +563,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
if (!pmd_present(*pmd)) if (!pmd_present(*pmd))
goto bad_access; goto bad_access;
pte = pte_offset_map_lock(mm, pmd, addr, &ptl); pte = pte_offset_map_lock(mm, pmd, addr, &ptl);
if (!pte_present(*pte) || !pte_dirty(*pte)) { if (!pte_present(*pte) || !pte_write(*pte) || !pte_dirty(*pte)) {
pte_unmap_unlock(pte, ptl); pte_unmap_unlock(pte, ptl);
goto bad_access; goto bad_access;
} }

2
arch/arm/mach-davinci/devices-da8xx.c
View File

@ -494,7 +494,7 @@ static struct platform_device da850_mcasp_device = {
.resource = da850_mcasp_resources, .resource = da850_mcasp_resources,
}; };
struct platform_device davinci_pcm_device = { static struct platform_device davinci_pcm_device = {
.name = "davinci-pcm-audio", .name = "davinci-pcm-audio",
.id = -1, .id = -1,
}; };

2
arch/arm/mach-davinci/devices.c
View File

@ -298,7 +298,7 @@ static void davinci_init_wdt(void)
/*-------------------------------------------------------------------------*/ /*-------------------------------------------------------------------------*/
struct platform_device davinci_pcm_device = { static struct platform_device davinci_pcm_device = {
.name = "davinci-pcm-audio", .name = "davinci-pcm-audio",
.id = -1, .id = -1,
}; };

7
arch/arm/mach-davinci/gpio.c
View File

@ -252,9 +252,11 @@ static struct irq_chip gpio_irqchip = {
static void static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc) gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{ {
struct davinci_gpio_regs __iomem *g = irq2regs(irq); struct davinci_gpio_regs __iomem *g;
u32 mask = 0xffff; u32 mask = 0xffff;
g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc);
/* we only care about one bank */ /* we only care about one bank */
if (irq & 1) if (irq & 1)
mask <<= 16; mask <<= 16;
@ -422,8 +424,7 @@ static int __init davinci_gpio_irq_setup(void)
/* set up all irqs in this bank */ /* set up all irqs in this bank */
irq_set_chained_handler(bank_irq, gpio_irq_handler); irq_set_chained_handler(bank_irq, gpio_irq_handler);
irq_set_chip_data(bank_irq, (__force void *)g); irq_set_handler_data(bank_irq, (__force void *)g);
irq_set_handler_data(bank_irq, (void *)irq);
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
irq_set_chip(irq, &gpio_irqchip); irq_set_chip(irq, &gpio_irqchip);

1
arch/arm/mach-footbridge/dc21285-timer.c
View File

@ -103,6 +103,7 @@ static void __init footbridge_timer_init(void)
clockevents_calc_mult_shift(ce, mem_fclk_21285, 5); clockevents_calc_mult_shift(ce, mem_fclk_21285, 5);
ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce); ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce);
ce->min_delta_ns = clockevent_delta2ns(0x000004, ce); ce->min_delta_ns = clockevent_delta2ns(0x000004, ce);
ce->cpumask = cpumask_of(smp_processor_id());
clockevents_register_device(ce); clockevents_register_device(ce);
} }

5
arch/arm/mach-footbridge/include/mach/debug-macro.S
View File

@ -26,6 +26,7 @@
#include <asm/hardware/debug-8250.S> #include <asm/hardware/debug-8250.S>
#else #else
#include <mach/hardware.h>
/* For EBSA285 debugging */ /* For EBSA285 debugging */
.equ dc21285_high, ARMCSR_BASE & 0xff000000 .equ dc21285_high, ARMCSR_BASE & 0xff000000
.equ dc21285_low, ARMCSR_BASE & 0x00ffffff .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
@ -36,8 +37,8 @@
.else .else
mov \rp, #0 mov \rp, #0
.endif .endif
orr \rv, \rp, #0x42000000 orr \rv, \rp, #dc21285_high
orr \rp, \rp, #dc21285_high orr \rp, \rp, #0x42000000
.endm .endm
.macro senduart,rd,rx .macro senduart,rd,rx

2
arch/arm/mach-mxs/ocotp.c
View File

@ -16,6 +16,8 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/mutex.h> #include <linux/mutex.h>
#include <asm/processor.h> /* for cpu_relax() */
#include <mach/mxs.h> #include <mach/mxs.h>
#define OCOTP_WORD_OFFSET 0x20 #define OCOTP_WORD_OFFSET 0x20

2
arch/arm/mach-u300/clock.h
View File

@ -31,7 +31,7 @@ struct clk {
bool reset; bool reset;
__u16 clk_val; __u16 clk_val;
__s8 usecount; __s8 usecount;
__u32 res_reg; void __iomem * res_reg;
__u16 res_mask; __u16 res_mask;
bool hw_ctrld; bool hw_ctrld;

22
arch/arm/mach-u300/include/mach/u300-regs.h
View File

@ -18,6 +18,12 @@
* the defines are used for setting up the I/O memory mapping. * the defines are used for setting up the I/O memory mapping.
*/ */
#ifdef __ASSEMBLER__
#define IOMEM(a) (a)
#else
#define IOMEM(a) (void __iomem *) a
#endif
/* NAND Flash CS0 */ /* NAND Flash CS0 */
#define U300_NAND_CS0_PHYS_BASE 0x80000000 #define U300_NAND_CS0_PHYS_BASE 0x80000000
@ -47,13 +53,6 @@
#define U300_SEMI_CONFIG_BASE 0x30000000 #define U300_SEMI_CONFIG_BASE 0x30000000
#endif #endif
/*
* All the following peripherals are specified at their PHYSICAL address,
* so if you need to access them (in the kernel), you MUST use the macros
* defined in <asm/io.h> to map to the IO_ADDRESS_AHB() IO_ADDRESS_FAST()
* etc.
*/
/* /*
* AHB peripherals * AHB peripherals
*/ */
@ -63,11 +62,11 @@
/* Vectored Interrupt Controller 0, servicing 32 interrupts */ /* Vectored Interrupt Controller 0, servicing 32 interrupts */
#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000) #define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
#define U300_INTCON0_VBASE (U300_AHB_PER_VIRT_BASE+0x1000) #define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
/* Vectored Interrupt Controller 1, servicing 32 interrupts */ /* Vectored Interrupt Controller 1, servicing 32 interrupts */
#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000) #define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
#define U300_INTCON1_VBASE (U300_AHB_PER_VIRT_BASE+0x2000) #define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
/* Memory Stick Pro (MSPRO) controller */ /* Memory Stick Pro (MSPRO) controller */
#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000) #define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
@ -115,7 +114,7 @@
/* SYSCON */ /* SYSCON */
#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000) #define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
#define U300_SYSCON_VBASE (U300_SLOW_PER_VIRT_BASE+0x1000) #define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
/* Watchdog */ /* Watchdog */
#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000) #define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
@ -125,7 +124,7 @@
/* APP side special timer */ /* APP side special timer */
#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000) #define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
#define U300_TIMER_APP_VBASE (U300_SLOW_PER_VIRT_BASE+0x4000) #define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
/* Keypad */ /* Keypad */
#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000) #define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
@ -181,5 +180,4 @@
* Virtual accessor macros for static devices * Virtual accessor macros for static devices
*/ */
#endif #endif

3
arch/arm/mach-u300/timer.c
View File

@ -411,8 +411,7 @@ static void __init u300_timer_init(void)
/* Use general purpose timer 2 as clock source */ /* Use general purpose timer 2 as clock source */
if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC, if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
"GPT2", rate, 300, 32, clocksource_mmio_readl_up)) "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
printk(KERN_ERR "timer: failed to initialize clock " pr_err("timer: failed to initialize U300 clock source\n");
"source %s\n", clocksource_u300_1mhz.name);
clockevents_calc_mult_shift(&clockevent_u300_1mhz, clockevents_calc_mult_shift(&clockevent_u300_1mhz,
rate, APPTIMER_MIN_RANGE); rate, APPTIMER_MIN_RANGE);

15
arch/arm/mach-vexpress/v2m.c
View File

@ -46,12 +46,6 @@ static struct map_desc v2m_io_desc[] __initdata = {
}, },
}; };
static void __init v2m_init_early(void)
{
ct_desc->init_early();
versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
}
static void __init v2m_timer_init(void) static void __init v2m_timer_init(void)
{ {
u32 scctrl; u32 scctrl;
@ -365,6 +359,13 @@ static struct clk_lookup v2m_lookups[] = {
}, },
}; };
static void __init v2m_init_early(void)
{
ct_desc->init_early();
clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
}
static void v2m_power_off(void) static void v2m_power_off(void)
{ {
if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0)) if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0))
@ -418,8 +419,6 @@ static void __init v2m_init(void)
{ {
int i; int i;
clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
platform_device_register(&v2m_pcie_i2c_device); platform_device_register(&v2m_pcie_i2c_device);
platform_device_register(&v2m_ddc_i2c_device); platform_device_register(&v2m_ddc_i2c_device);
platform_device_register(&v2m_flash_device); platform_device_register(&v2m_flash_device);

17
arch/arm/mm/context.c
View File

@ -24,7 +24,9 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm);
/* /*
* We fork()ed a process, and we need a new context for the child * We fork()ed a process, and we need a new context for the child
* to run in. * to run in. We reserve version 0 for initial tasks so we will
* always allocate an ASID. The ASID 0 is reserved for the TTBR
* register changing sequence.
*/ */
void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{ {
@ -34,11 +36,8 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
static void flush_context(void) static void flush_context(void)
{ {
u32 ttb; /* set the reserved ASID before flushing the TLB */
/* Copy TTBR1 into TTBR0 */ asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0));
asm volatile("mrc p15, 0, %0, c2, c0, 1\n"
"mcr p15, 0, %0, c2, c0, 0"
: "=r" (ttb));
isb(); isb();
local_flush_tlb_all(); local_flush_tlb_all();
if (icache_is_vivt_asid_tagged()) { if (icache_is_vivt_asid_tagged()) {
@ -94,7 +93,7 @@ static void reset_context(void *info)
return; return;
smp_rmb(); smp_rmb();
asid = cpu_last_asid + cpu; asid = cpu_last_asid + cpu + 1;
flush_context(); flush_context();
set_mm_context(mm, asid); set_mm_context(mm, asid);
@ -144,13 +143,13 @@ void __new_context(struct mm_struct *mm)
* to start a new version and flush the TLB. * to start a new version and flush the TLB.
*/ */
if (unlikely((asid & ~ASID_MASK) == 0)) { if (unlikely((asid & ~ASID_MASK) == 0)) {
asid = cpu_last_asid + smp_processor_id(); asid = cpu_last_asid + smp_processor_id() + 1;
flush_context(); flush_context();
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
smp_wmb(); smp_wmb();
smp_call_function(reset_context, NULL, 1); smp_call_function(reset_context, NULL, 1);
#endif #endif
cpu_last_asid += NR_CPUS - 1; cpu_last_asid += NR_CPUS;
} }
set_mm_context(mm, asid); set_mm_context(mm, asid);

12
arch/arm/mm/init.c
View File

@ -330,6 +330,12 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
memblock_reserve(__pa(_stext), _end - _stext); memblock_reserve(__pa(_stext), _end - _stext);
#endif #endif
#ifdef CONFIG_BLK_DEV_INITRD #ifdef CONFIG_BLK_DEV_INITRD
if (phys_initrd_size &&
!memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n",
phys_initrd_start, phys_initrd_size);
phys_initrd_start = phys_initrd_size = 0;
}
if (phys_initrd_size && if (phys_initrd_size &&
memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) { memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n", pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
@ -635,7 +641,8 @@ void __init mem_init(void)
" modules : 0x%08lx - 0x%08lx (%4ld MB)\n" " modules : 0x%08lx - 0x%08lx (%4ld MB)\n"
" .init : 0x%p" " - 0x%p" " (%4d kB)\n" " .init : 0x%p" " - 0x%p" " (%4d kB)\n"
" .text : 0x%p" " - 0x%p" " (%4d kB)\n" " .text : 0x%p" " - 0x%p" " (%4d kB)\n"
" .data : 0x%p" " - 0x%p" " (%4d kB)\n", " .data : 0x%p" " - 0x%p" " (%4d kB)\n"
" .bss : 0x%p" " - 0x%p" " (%4d kB)\n",
MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
(PAGE_SIZE)), (PAGE_SIZE)),
@ -657,7 +664,8 @@ void __init mem_init(void)
MLK_ROUNDUP(__init_begin, __init_end), MLK_ROUNDUP(__init_begin, __init_end),
MLK_ROUNDUP(_text, _etext), MLK_ROUNDUP(_text, _etext),
MLK_ROUNDUP(_sdata, _edata)); MLK_ROUNDUP(_sdata, _edata),
MLK_ROUNDUP(__bss_start, __bss_stop));
#undef MLK #undef MLK
#undef MLM #undef MLM

2
arch/arm/mm/proc-arm7tdmi.S
View File

@ -146,7 +146,7 @@ __arm7tdmi_proc_info:
.long 0 .long 0
.long 0 .long 0
.long v4_cache_fns .long v4_cache_fns
.size __arm7tdmi_proc_info, . - __arm7dmi_proc_info .size __arm7tdmi_proc_info, . - __arm7tdmi_proc_info
.type __triscenda7_proc_info, #object .type __triscenda7_proc_info, #object
__triscenda7_proc_info: __triscenda7_proc_info:

2
arch/arm/mm/proc-arm9tdmi.S
View File

@ -116,7 +116,7 @@ __arm9tdmi_proc_info:
.long 0 .long 0
.long 0 .long 0
.long v4_cache_fns .long v4_cache_fns
.size __arm9tdmi_proc_info, . - __arm9dmi_proc_info .size __arm9tdmi_proc_info, . - __arm9tdmi_proc_info
.type __p2001_proc_info, #object .type __p2001_proc_info, #object
__p2001_proc_info: __p2001_proc_info:

10
arch/arm/mm/proc-v7.S
View File

@ -108,16 +108,18 @@ ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_ARM_ERRATA_430973 #ifdef CONFIG_ARM_ERRATA_430973
mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
#endif #endif
mrc p15, 0, r2, c2, c0, 1 @ load TTB 1 #ifdef CONFIG_ARM_ERRATA_754322
mcr p15, 0, r2, c2, c0, 0 @ into TTB 0 dsb
#endif
mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
isb
1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
isb isb
#ifdef CONFIG_ARM_ERRATA_754322 #ifdef CONFIG_ARM_ERRATA_754322
dsb dsb
#endif #endif
mcr p15, 0, r1, c13, c0, 1 @ set context ID mcr p15, 0, r1, c13, c0, 1 @ set context ID
isb isb
mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
isb
#endif #endif
mov pc, lr mov pc, lr
ENDPROC(cpu_v7_switch_mm) ENDPROC(cpu_v7_switch_mm)

6
arch/arm/plat-mxc/devices/platform-imx-dma.c
View File

@ -139,7 +139,7 @@ static struct sdma_script_start_addrs addr_imx35_to2 = {
#endif #endif
#ifdef CONFIG_SOC_IMX51 #ifdef CONFIG_SOC_IMX51
static struct sdma_script_start_addrs addr_imx51_to1 = { static struct sdma_script_start_addrs addr_imx51 = {
.ap_2_ap_addr = 642, .ap_2_ap_addr = 642,
.uart_2_mcu_addr = 817, .uart_2_mcu_addr = 817,
.mcu_2_app_addr = 747, .mcu_2_app_addr = 747,
@ -196,7 +196,9 @@ static int __init imxXX_add_imx_dma(void)
#if defined(CONFIG_SOC_IMX51) #if defined(CONFIG_SOC_IMX51)
if (cpu_is_mx51()) { if (cpu_is_mx51()) {
imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1; int to_version = mx51_revision() >> 4;
imx51_imx_sdma_data.pdata.to_version = to_version;
imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51;
ret = imx_add_imx_sdma(&imx51_imx_sdma_data); ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
} else } else
#endif #endif

10
drivers/mmc/host/mmci.c
View File

@ -1144,8 +1144,16 @@ static int __devinit mmci_probe(struct amba_device *dev,
else if (ret != -ENOSYS) else if (ret != -ENOSYS)
goto err_gpio_cd; goto err_gpio_cd;
/*
* A gpio pin that will detect cards when inserted and removed
* will most likely want to trigger on the edges if it is
* 0 when ejected and 1 when inserted (or mutatis mutandis
* for the inverted case) so we request triggers on both
* edges.
*/
ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
mmci_cd_irq, 0, mmci_cd_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
DRIVER_NAME " (cd)", host); DRIVER_NAME " (cd)", host);
if (ret >= 0) if (ret >= 0)
host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);