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drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch] 

Add new files i915_ioctl.[ch] to hold small ioctls that are out of place
everywhere else, and not big enough to warrant a file of their own. For
starters, it's just for i915_reg_read_ioctl() that's a bit high level
for a low level implementation that intel_uncore.[ch] is.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220120113346.3214745-1-jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2022-01-20 13:33:46 +02:00
parent 5de6a3de99
commit 198bca9340
6 changed files with 111 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/i915/Makefile
View File

@ -32,8 +32,9 @@ subdir-ccflags-y += -I$(srctree)/$(src)
# core driver code
i915-y += i915_driver.o \
i915_config.o \
i915_irq.o \
i915_getparam.o \
i915_ioctl.o \
i915_irq.o \
i915_mitigations.o \
i915_module.o \
i915_params.o \

1
drivers/gpu/drm/i915/i915_driver.c
View File

@ -76,6 +76,7 @@
#include "i915_drv.h"
#include "i915_getparam.h"
#include "i915_ioc32.h"
#include "i915_ioctl.h"
#include "i915_irq.h"
#include "i915_memcpy.h"
#include "i915_perf.h"

3
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1716,9 +1716,6 @@ mkwrite_device_info(struct drm_i915_private *dev_priv)
return (struct intel_device_info *)INTEL_INFO(dev_priv);
}
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
if (GRAPHICS_VER(i915) >= 11)

94
drivers/gpu/drm/i915/i915_ioctl.c Normal file
View File

@ -0,0 +1,94 @@
// SPDX-License-Identifier: MIT
/*
* Copyright © 2022 Intel Corporation
*/
#include "gt/intel_engine_regs.h"
#include "i915_drv.h"
#include "i915_gem.h"
#include "i915_ioctl.h"
#include "i915_reg.h"
#include "intel_runtime_pm.h"
#include "intel_uncore.h"
/*
* This file is for small ioctl functions that are out of place everywhere else,
* and not big enough to warrant a file of their own.
*
* This is not the dumping ground for random ioctls.
*/
struct reg_whitelist {
i915_reg_t offset_ldw;
i915_reg_t offset_udw;
u8 min_graphics_ver;
u8 max_graphics_ver;
u8 size;
};
static const struct reg_whitelist reg_read_whitelist[] = {
{
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.min_graphics_ver = 4,
.max_graphics_ver = 12,
.size = 8
}
};
int i915_reg_read_ioctl(struct drm_device *dev,
void *data, struct drm_file *unused)
{
struct drm_i915_private *i915 = to_i915(dev);
struct intel_uncore *uncore = &i915->uncore;
struct drm_i915_reg_read *reg = data;
struct reg_whitelist const *entry;
intel_wakeref_t wakeref;
unsigned int flags;
int remain;
int ret = 0;
entry = reg_read_whitelist;
remain = ARRAY_SIZE(reg_read_whitelist);
while (remain) {
u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
GEM_BUG_ON(!is_power_of_2(entry->size));
GEM_BUG_ON(entry->size > 8);
GEM_BUG_ON(entry_offset & (entry->size - 1));
if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
entry_offset == (reg->offset & -entry->size))
break;
entry++;
remain--;
}
if (!remain)
return -EINVAL;
flags = reg->offset & (entry->size - 1);
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
reg->val = intel_uncore_read64_2x32(uncore,
entry->offset_ldw,
entry->offset_udw);
else if (entry->size == 8 && flags == 0)
reg->val = intel_uncore_read64(uncore,
entry->offset_ldw);
else if (entry->size == 4 && flags == 0)
reg->val = intel_uncore_read(uncore, entry->offset_ldw);
else if (entry->size == 2 && flags == 0)
reg->val = intel_uncore_read16(uncore,
entry->offset_ldw);
else if (entry->size == 1 && flags == 0)
reg->val = intel_uncore_read8(uncore,
entry->offset_ldw);
else
ret = -EINVAL;
}
return ret;
}

14
drivers/gpu/drm/i915/i915_ioctl.h Normal file
View File

@ -0,0 +1,14 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef __I915_IOCTL_H__
#define __I915_IOCTL_H__
struct drm_device;
struct drm_file;
int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
#endif /* __I915_IOCTL_H__ */

70
drivers/gpu/drm/i915/intel_uncore.c
View File

@ -2265,76 +2265,6 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
uncore_mmio_cleanup(uncore);
}
static const struct reg_whitelist {
i915_reg_t offset_ldw;
i915_reg_t offset_udw;
u8 min_graphics_ver;
u8 max_graphics_ver;
u8 size;
} reg_read_whitelist[] = { {
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.min_graphics_ver = 4,
.max_graphics_ver = 12,
.size = 8
} };
int i915_reg_read_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
struct intel_uncore *uncore = &i915->uncore;
struct drm_i915_reg_read *reg = data;
struct reg_whitelist const *entry;
intel_wakeref_t wakeref;
unsigned int flags;
int remain;
int ret = 0;
entry = reg_read_whitelist;
remain = ARRAY_SIZE(reg_read_whitelist);
while (remain) {
u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
GEM_BUG_ON(!is_power_of_2(entry->size));
GEM_BUG_ON(entry->size > 8);
GEM_BUG_ON(entry_offset & (entry->size - 1));
if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) &&
entry_offset == (reg->offset & -entry->size))
break;
entry++;
remain--;
}
if (!remain)
return -EINVAL;
flags = reg->offset & (entry->size - 1);
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
reg->val = intel_uncore_read64_2x32(uncore,
entry->offset_ldw,
entry->offset_udw);
else if (entry->size == 8 && flags == 0)
reg->val = intel_uncore_read64(uncore,
entry->offset_ldw);
else if (entry->size == 4 && flags == 0)
reg->val = intel_uncore_read(uncore, entry->offset_ldw);
else if (entry->size == 2 && flags == 0)
reg->val = intel_uncore_read16(uncore,
entry->offset_ldw);
else if (entry->size == 1 && flags == 0)
reg->val = intel_uncore_read8(uncore,
entry->offset_ldw);
else
ret = -EINVAL;
}
return ret;
}
/**
* __intel_wait_for_register_fw - wait until register matches expected state
* @uncore: the struct intel_uncore