Amlogic 32-bit DT changes for v4.13 (round 2)
- greatly expands DT clock support for meson8b -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJZTDWYAAoJEFk3GJrT+8ZlGwsP/0K7Mb81/wkne6Yr7FOQ/PTm QcPG9QGhj/2QyafiAEu5REeg/oraHxt/HCAC9uz7jM0CfrdYLD0imoMTOgqaIGZc BtvdJthSRUZPc91ou6vP527MB46ipTtP/69Ed/hmkSALm9QAhs430HsXfmmU7KnS M0dbQ1KOqQ4Hd/zup3D1LfUlsaOcuiiu73Ys3Xg5zBAq8QWJypLhZL7f9dvVYCQ+ lqEtsjUt/qNvky72oKsSZX6Eb2gHKtC38fOVeYq3Z5xatU2UNWlEBGxmfTyFQP+E T3wBvCVgSPmqW0wD9yGdfqKtH7ZXJ1OBE/21pxjPLq1Rb45kC26jC9FMDOb0RS3w jaPzinjCcJ0AR5wUojmy7xbaVBrAESaldtj32Fxz4LIe6qPUB8AAiUsTAzwve/Bk 17RP5Zf2BsBcmfsai+HYc6zGCwqC2pbmotuX3Sfw/CeE3sRhWqtpkixV9xsidM5f oR7bBsAjAhzRJ+SvMiJ0kPa9iNQdCgE3C2quIns7F35jwuWMAckGe6BeJ6RbX1ZK Mrzq4r7Q1utYldYfBgus/1Tf/RW+iwqGcyarhq6GAFcjx9siKF4lb5tXt237xwK2 vP+KTRAAqii3F0+sUkzKZV2/RpqRDslmCPuq2mQNRfCtm+Px97vl+saRduz2R2jd vcKSfM8Vj2voxITL3nNz =o8Zj -----END PGP SIGNATURE----- Merge tag 'amlogic-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Merge "Amlogic 32-bit DT changes for v4.13 (round 2)" from Kevin Hilman: - greatly expands DT clock support for meson8b * tag 'amlogic-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (22 commits) ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b ARM: dts: meson8b: add the SCU device node ARM: dts: meson: add USB support on Meson8 and Meson8b ARM: dts: meson: add the hardware random number generator ARM: dts: meson8: add reserved memory zones ARM: dts: meson: add the SAR ADC ARM: dts: meson8: add the pins for the SDIO controller ARM: dts: meson8: add the PWM_E and PWM_F pins ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros ARM: dts: meson: use C preprocessor friendly include syntax ARM: dts: meson8: fix the IR receiver pins clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks clk: meson-gxbb: un-export the CPU clock clk: meson-gxbb: expose UART clocks clk: meson-gxbb: expose SPICC gate clk: meson-gxbb: expose spdif master clock ...
This commit is contained in:
Arnd Bergmann
commit
1964babb26
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@ -45,6 +45,8 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/include/ "skeleton.dtsi"
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/ {
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@ -78,45 +80,72 @@
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#size-cells = <1>;
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ranges = <0x0 0xc1100000 0x200000>;
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hwrng: rng@8100 {
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compatible = "amlogic,meson-rng";
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reg = <0x8100 0x8>;
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};
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uart_A: serial@84c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x84c0 0x18>;
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interrupts = <0 26 1>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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uart_B: serial@84dc {
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compatible = "amlogic,meson-uart";
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reg = <0x84dc 0x18>;
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interrupts = <0 75 1>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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i2c_A: i2c@8500 {
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compatible = "amlogic,meson6-i2c";
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reg = <0x8500 0x20>;
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interrupts = <0 21 1>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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saradc: adc@8680 {
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compatible = "amlogic,meson-saradc";
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reg = <0x8680 0x34>;
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#io-channel-cells = <1>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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uart_C: serial@8700 {
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compatible = "amlogic,meson-uart";
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reg = <0x8700 0x18>;
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interrupts = <0 93 1>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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i2c_B: i2c@87c0 {
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compatible = "amlogic,meson6-i2c";
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reg = <0x87c0 0x20>;
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interrupts = <0 128 1>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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usb0_phy: phy@8800 {
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compatible = "amlogic,meson-mx-usb2-phy";
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#phy-cells = <0>;
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reg = <0x8800 0x20>;
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status = "disabled";
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};
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usb1_phy: phy@8820 {
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compatible = "amlogic,meson-mx-usb2-phy";
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#phy-cells = <0>;
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reg = <0x8820 0x20>;
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status = "disabled";
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};
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spifc: spi@8c80 {
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compatible = "amlogic,meson6-spifc";
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reg = <0x8c80 0x80>;
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@ -128,13 +157,13 @@
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wdt: watchdog@9900 {
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compatible = "amlogic,meson6-wdt";
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reg = <0x9900 0x8>;
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interrupts = <0 0 1>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
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};
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timer@9940 {
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compatible = "amlogic,meson6-timer";
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reg = <0x9940 0x18>;
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interrupts = <0 10 1>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>;
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};
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};
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@ -148,32 +177,56 @@
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ir_receiver: ir-receiver@480 {
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compatible= "amlogic,meson6-ir";
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reg = <0x480 0x20>;
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interrupts = <0 15 1>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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uart_AO: serial@4c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x4c0 0x18>;
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interrupts = <0 90 1>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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i2c_AO: i2c@500 {
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compatible = "amlogic,meson6-i2c";
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reg = <0x500 0x20>;
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interrupts = <0 92 1>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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usb0: usb@c9040000 {
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compatible = "snps,dwc2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc9040000 0x40000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>;
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phys = <&usb0_phy>;
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phy-names = "usb2-phy";
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dr_mode = "host";
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status = "disabled";
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};
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usb1: usb@c90c0000 {
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compatible = "snps,dwc2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc90c0000 0x40000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
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phys = <&usb1_phy>;
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phy-names = "usb2-phy";
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dr_mode = "host";
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status = "disabled";
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};
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ethmac: ethernet@c9410000 {
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compatible = "amlogic,meson6-dwmac", "snps,dwmac";
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reg = <0xc9410000 0x10000
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0xc1108108 0x4>;
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interrupts = <0 8 1>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "macirq";
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status = "disabled";
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};
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@ -46,7 +46,7 @@
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*/
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/dts-v1/;
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/include/ "meson6.dtsi"
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#include "meson6.dtsi"
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/ {
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model = "Geniatech ATV1200";
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@ -45,7 +45,7 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/include/ "meson.dtsi"
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#include "meson.dtsi"
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/ {
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model = "Amlogic Meson6 SoC";
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@ -45,7 +45,7 @@
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <dt-bindings/gpio/meson8-gpio.h>
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/include/ "meson.dtsi"
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#include "meson.dtsi"
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/ {
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model = "Amlogic Meson8 SoC";
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@ -83,6 +83,38 @@
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reg = <0x203>;
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* 2 MiB reserved for Hardware ROM Firmware? */
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hwrom@0 {
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reg = <0x0 0x200000>;
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no-map;
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};
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/*
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* 1 MiB reserved for the "ARM Power Firmware": this is ARM
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* code which is responsible for system suspend. It loads a
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* piece of ARC code ("arc_power" in the vendor u-boot tree)
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* into SRAM, executes that and shuts down the (last) ARM core.
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* The arc_power firmware then checks various wakeup sources
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* (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
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* simply the power key) and re-starts the ARM core once it
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* detects a wakeup request.
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*/
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power-firmware@4f00000 {
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reg = <0x4f00000 0x100000>;
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no-map;
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};
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};
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scu@c4300000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xc4300000 0x100>;
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};
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}; /* end of / */
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&aobus {
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@ -116,6 +148,20 @@
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function = "i2c_mst_ao";
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};
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};
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ir_recv_pins: remote {
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mux {
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groups = "remote_input";
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function = "remote";
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};
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};
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pwm_f_ao_pins: pwm-f-ao {
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mux {
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groups = "pwm_f_ao";
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function = "pwm_f_ao";
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};
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};
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};
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};
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@ -144,6 +190,30 @@
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gpio-ranges = <&pinctrl_cbus 0 0 120>;
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};
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sd_a_pins: sd-a {
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mux {
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groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
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"sd_d3_a", "sd_clk_a", "sd_cmd_a";
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function = "sd_a";
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};
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};
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sd_b_pins: sd-b {
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mux {
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groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
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"sd_d3_b", "sd_clk_b", "sd_cmd_b";
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function = "sd_b";
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};
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};
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sd_c_pins: sd-c {
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mux {
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groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
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"sd_d3_c", "sd_clk_c", "sd_cmd_c";
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function = "sd_c";
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};
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};
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spi_nor_pins: nor {
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mux {
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groups = "nor_d", "nor_q", "nor_c", "nor_cs";
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@ -151,13 +221,6 @@
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};
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};
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ir_recv_pins: remote {
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mux {
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groups = "remote_input";
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function = "remote";
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};
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};
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eth_pins: ethernet {
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mux {
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groups = "eth_tx_clk_50m", "eth_tx_en",
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@ -168,14 +231,27 @@
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function = "ethernet";
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};
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};
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pwm_e_pins: pwm-e {
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mux {
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groups = "pwm_e";
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function = "pwm_e";
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};
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};
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};
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};
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ðmac {
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clocks = <&clkc CLKID_CLK81>;
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clocks = <&clkc CLKID_ETH>;
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clock-names = "stmmaceth";
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};
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&hwrng {
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compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
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clocks = <&clkc CLKID_RNG0>;
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clock-names = "core";
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};
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&i2c_AO {
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clocks = <&clkc CLKID_CLK81>;
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};
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@ -194,6 +270,14 @@
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arm,filter-ranges = <0x100000 0xc0000000>;
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};
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&saradc {
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compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
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clocks = <&clkc CLKID_XTAL>,
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<&clkc CLKID_SAR_ADC>,
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<&clkc CLKID_SANA>;
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clock-names = "clkin", "core", "sana";
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};
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&spifc {
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clocks = <&clkc CLKID_CLK81>;
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};
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@ -213,3 +297,27 @@
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&uart_C {
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clocks = <&clkc CLKID_CLK81>;
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||||
};
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|
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&usb0 {
|
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compatible = "amlogic,meson8-usb", "snps,dwc2";
|
||||
clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
|
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clock-names = "otg";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
compatible = "amlogic,meson8-usb", "snps,dwc2";
|
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clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
|
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clock-names = "otg";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
|
||||
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
|
||||
clock-names = "usb_general", "usb";
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
|
||||
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
|
||||
clock-names = "usb_general", "usb";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -82,6 +82,11 @@
|
|||
reg = <0x203>;
|
||||
};
|
||||
};
|
||||
|
||||
scu@c4300000 {
|
||||
compatible = "arm,cortex-a5-scu";
|
||||
reg = <0xc4300000 0x100>;
|
||||
};
|
||||
}; /* end of / */
|
||||
|
||||
&aobus {
|
||||
|
|
@ -171,12 +176,31 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
clocks = <&clkc CLKID_ETH>;
|
||||
clock-names = "stmmaceth";
|
||||
};
|
||||
|
||||
&hwrng {
|
||||
compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
|
||||
clocks = <&clkc CLKID_RNG0>;
|
||||
clock-names = "core";
|
||||
};
|
||||
|
||||
&L2 {
|
||||
arm,data-latency = <3 3 3>;
|
||||
arm,tag-latency = <2 2 2>;
|
||||
arm,filter-ranges = <0x100000 0xc0000000>;
|
||||
};
|
||||
|
||||
&saradc {
|
||||
compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
|
||||
clocks = <&clkc CLKID_XTAL>,
|
||||
<&clkc CLKID_SAR_ADC>,
|
||||
<&clkc CLKID_SANA>;
|
||||
clock-names = "clkin", "core", "sana";
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
clocks = <&clkc CLKID_CLK81>;
|
||||
};
|
||||
|
|
@ -192,3 +216,29 @@
|
|||
&uart_C {
|
||||
clocks = <&clkc CLKID_CLK81>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
compatible = "amlogic,meson8b-usb", "snps,dwc2";
|
||||
clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
|
||||
clock-names = "otg";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
compatible = "amlogic,meson8b-usb", "snps,dwc2";
|
||||
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
|
||||
clock-names = "otg";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
|
||||
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
|
||||
clock-names = "usb_general", "usb";
|
||||
resets = <&reset RESET_USB_OTG>;
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
|
||||
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
|
||||
clock-names = "usb_general", "usb";
|
||||
resets = <&reset RESET_USB_OTG>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@
|
|||
* to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
|
||||
*/
|
||||
#define CLKID_SYS_PLL 0
|
||||
/* CLKID_CPUCLK */
|
||||
#define CLKID_CPUCLK 1
|
||||
/* CLKID_HDMI_PLL */
|
||||
#define CLKID_FIXED_PLL 3
|
||||
/* CLKID_FCLK_DIV2 */
|
||||
|
|
@ -191,12 +191,12 @@
|
|||
#define CLKID_ISA 18
|
||||
#define CLKID_PL301 19
|
||||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC 21
|
||||
/* CLKID_SPICC */
|
||||
/* CLKID_I2C */
|
||||
/* #define CLKID_SAR_ADC */
|
||||
#define CLKID_SMART_CARD 24
|
||||
/* CLKID_RNG0 */
|
||||
#define CLKID_UART0 26
|
||||
/* CLKID_UART0 */
|
||||
#define CLKID_SDHC 27
|
||||
#define CLKID_STREAM 28
|
||||
#define CLKID_ASYNC_FIFO 29
|
||||
|
|
@ -209,7 +209,7 @@
|
|||
/* CLKID_ETH */
|
||||
#define CLKID_DEMUX 37
|
||||
/* CLKID_AIU_GLUE */
|
||||
#define CLKID_IEC958 39
|
||||
/* CLKID_IEC958 */
|
||||
/* CLKID_I2S_OUT */
|
||||
#define CLKID_AMCLK 41
|
||||
#define CLKID_AIFIFO2 42
|
||||
|
|
@ -218,7 +218,7 @@
|
|||
#define CLKID_ADC 45
|
||||
#define CLKID_BLKMV 46
|
||||
/* CLKID_AIU */
|
||||
#define CLKID_UART1 48
|
||||
/* CLKID_UART1 */
|
||||
#define CLKID_G2D 49
|
||||
/* CLKID_USB0 */
|
||||
/* CLKID_USB1 */
|
||||
|
|
@ -238,7 +238,7 @@
|
|||
/* CLKID_USB0_DDR_BRIDGE */
|
||||
#define CLKID_MMC_PCLK 66
|
||||
#define CLKID_DVIN 67
|
||||
#define CLKID_UART2 68
|
||||
/* CLKID_UART2 */
|
||||
/* #define CLKID_SANA */
|
||||
#define CLKID_VPU_INTR 70
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
|
||||
|
|
@ -251,7 +251,7 @@
|
|||
#define CLKID_GCLK_VENCI_INT 78
|
||||
#define CLKID_DAC_CLK 79
|
||||
/* CLKID_AOCLK_GATE */
|
||||
#define CLKID_IEC958_GATE 81
|
||||
/* CLKID_IEC958_GATE */
|
||||
#define CLKID_ENC480P 82
|
||||
#define CLKID_RNG1 83
|
||||
#define CLKID_GCLK_VENCI_INT1 84
|
||||
|
|
@ -277,13 +277,13 @@
|
|||
#define CLKID_MALI_1_DIV 104
|
||||
/* CLKID_MALI_1 */
|
||||
/* CLKID_MALI */
|
||||
#define CLKID_CTS_AMCLK 107
|
||||
/* CLKID_CTS_AMCLK */
|
||||
#define CLKID_CTS_AMCLK_SEL 108
|
||||
#define CLKID_CTS_AMCLK_DIV 109
|
||||
#define CLKID_CTS_MCLK_I958 110
|
||||
/* CLKID_CTS_MCLK_I958 */
|
||||
#define CLKID_CTS_MCLK_I958_SEL 111
|
||||
#define CLKID_CTS_MCLK_I958_DIV 112
|
||||
#define CLKID_CTS_I958 113
|
||||
/* CLKID_CTS_I958 */
|
||||
|
||||
#define NR_CLKS 114
|
||||
|
||||
|
|
|
|||
|
|
@ -87,20 +87,20 @@
|
|||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC 21
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_SAR_ADC 23
|
||||
/* #define CLKID_SAR_ADC */
|
||||
#define CLKID_SMART_CARD 24
|
||||
#define CLKID_RNG0 25
|
||||
/* #define CLKID_RNG0 */
|
||||
#define CLKID_UART0 26
|
||||
#define CLKID_SDHC 27
|
||||
#define CLKID_STREAM 28
|
||||
#define CLKID_ASYNC_FIFO 29
|
||||
#define CLKID_SDIO 30
|
||||
/* #define CLKID_SDIO */
|
||||
#define CLKID_ABUF 31
|
||||
#define CLKID_HIU_IFACE 32
|
||||
#define CLKID_ASSIST_MISC 33
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_I2S_SPDIF 35
|
||||
#define CLKID_ETH 36
|
||||
/* #define CLKID_ETH */
|
||||
#define CLKID_DEMUX 37
|
||||
#define CLKID_AIU_GLUE 38
|
||||
#define CLKID_IEC958 39
|
||||
|
|
@ -114,12 +114,12 @@
|
|||
#define CLKID_AIU 47
|
||||
#define CLKID_UART1 48
|
||||
#define CLKID_G2D 49
|
||||
#define CLKID_USB0 50
|
||||
#define CLKID_USB1 51
|
||||
/* #define CLKID_USB0 */
|
||||
/* #define CLKID_USB1 */
|
||||
#define CLKID_RESET 52
|
||||
#define CLKID_NAND 53
|
||||
#define CLKID_DOS_PARSER 54
|
||||
#define CLKID_USB 55
|
||||
/* #define CLKID_USB */
|
||||
#define CLKID_VDIN1 56
|
||||
#define CLKID_AHB_ARB0 57
|
||||
#define CLKID_EFUSE 58
|
||||
|
|
@ -128,12 +128,12 @@
|
|||
#define CLKID_AHB_CTRL_BUS 61
|
||||
#define CLKID_HDMI_INTR_SYNC 62
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
#define CLKID_USB1_DDR_BRIDGE 64
|
||||
#define CLKID_USB0_DDR_BRIDGE 65
|
||||
/* CLKID_USB1_DDR_BRIDGE */
|
||||
/* CLKID_USB0_DDR_BRIDGE */
|
||||
#define CLKID_MMC_PCLK 66
|
||||
#define CLKID_DVIN 67
|
||||
#define CLKID_UART2 68
|
||||
#define CLKID_SANA 69
|
||||
/* #define CLKID_SANA */
|
||||
#define CLKID_VPU_INTR 70
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
|
||||
#define CLKID_CLK81_A9 72
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@
|
|||
#ifndef __GXBB_CLKC_H
|
||||
#define __GXBB_CLKC_H
|
||||
|
||||
#define CLKID_CPUCLK 1
|
||||
#define CLKID_HDMI_PLL 2
|
||||
#define CLKID_FCLK_DIV2 4
|
||||
#define CLKID_FCLK_DIV3 5
|
||||
|
|
@ -13,24 +12,30 @@
|
|||
#define CLKID_GP0_PLL 9
|
||||
#define CLKID_CLK81 12
|
||||
#define CLKID_MPLL2 15
|
||||
#define CLKID_SPICC 21
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_SAR_ADC 23
|
||||
#define CLKID_RNG0 25
|
||||
#define CLKID_UART0 26
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_AIU_GLUE 38
|
||||
#define CLKID_IEC958 39
|
||||
#define CLKID_I2S_OUT 40
|
||||
#define CLKID_MIXER_IFACE 44
|
||||
#define CLKID_AIU 47
|
||||
#define CLKID_UART1 48
|
||||
#define CLKID_USB0 50
|
||||
#define CLKID_USB1 51
|
||||
#define CLKID_USB 55
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
#define CLKID_USB1_DDR_BRIDGE 64
|
||||
#define CLKID_USB0_DDR_BRIDGE 65
|
||||
#define CLKID_UART2 68
|
||||
#define CLKID_SANA 69
|
||||
#define CLKID_GCLK_VENCI_INT0 77
|
||||
#define CLKID_AOCLK_GATE 80
|
||||
#define CLKID_IEC958_GATE 81
|
||||
#define CLKID_AO_I2C 93
|
||||
#define CLKID_SD_EMMC_A 94
|
||||
#define CLKID_SD_EMMC_B 95
|
||||
|
|
@ -42,5 +47,8 @@
|
|||
#define CLKID_MALI_1_SEL 103
|
||||
#define CLKID_MALI_1 105
|
||||
#define CLKID_MALI 106
|
||||
#define CLKID_CTS_AMCLK 107
|
||||
#define CLKID_CTS_MCLK_I958 110
|
||||
#define CLKID_CTS_I958 113
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -21,5 +21,15 @@
|
|||
#define CLKID_ZERO 13
|
||||
#define CLKID_MPEG_SEL 14
|
||||
#define CLKID_MPEG_DIV 15
|
||||
#define CLKID_SAR_ADC 23
|
||||
#define CLKID_RNG0 25
|
||||
#define CLKID_SDIO 30
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_USB0 50
|
||||
#define CLKID_USB1 51
|
||||
#define CLKID_USB 55
|
||||
#define CLKID_USB1_DDR_BRIDGE 64
|
||||
#define CLKID_USB0_DDR_BRIDGE 65
|
||||
#define CLKID_SANA 69
|
||||
|
||||
#endif /* __MESON8B_CLKC_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue