This pull request adds CPUFreq support for DA850 boards in device-tree

boot using the generic CPUFREQ_DT driver.
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Merge tag 'davinci-for-v5.3/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into arm/dt

This pull request adds CPUFreq support for DA850 boards in device-tree
boot using the generic CPUFREQ_DT driver.

* tag 'davinci-for-v5.3/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci_all_defconfig: Enable CPUFREQ_DT
  ARM: dts: da850-evm: enable cpufreq
  ARM: dts: da850-lcdk: enable cpufreq
  ARM: dts: da850-lego-ev3: enable cpufreq
  ARM: dts: da850: add cpu node and operating points to DT

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-06-25 04:37:18 -07:00
commit 19339e6a22
5 changed files with 130 additions and 0 deletions

View File

@ -188,6 +188,19 @@
};
};
&cpu {
cpu-supply = <&vdcdc3_reg>;
};
/*
* The standard da850-evm kits and SOM's are 375MHz so enable this operating
* point by default. Higher frequencies must be enabled for custom boards with
* other variants of the SoC.
*/
&opp_375 {
status = "okay";
};
&sata {
status = "okay";
};

View File

@ -154,12 +154,48 @@
};
};
};
cvdd: regulator0 {
compatible = "regulator-fixed";
regulator-name = "cvdd";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
};
&ref_clk {
clock-frequency = <24000000>;
};
&cpu {
cpu-supply = <&cvdd>;
};
/*
* LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are
* valid. Unfortunately due to a problem with the DA8XX OHCI controller, we
* can't enable more than one OPP by default, since the controller sometimes
* becomes unresponsive after a transition. Fix the frequency at 456 MHz.
*/
&opp_100 {
status = "disabled";
};
&opp_200 {
status = "disabled";
};
&opp_300 {
status = "disabled";
};
&opp_456 {
status = "okay";
};
&pmx_core {
status = "okay";

View File

@ -122,6 +122,15 @@
amp-supply = <&amp>;
};
cvdd: regulator0 {
compatible = "regulator-fixed";
regulator-name = "cvdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
/*
* This is a 5V current limiting regulator that is shared by USB,
* the sensor (input) ports, the motor (output) ports and the A/DC.
@ -201,6 +210,27 @@
clock-frequency = <24000000>;
};
&cpu {
cpu-supply = <&cvdd>;
};
/* since we have a fixed regulator, we can't run at these points */
&opp_100 {
status = "disabled";
};
&opp_200 {
status = "disabled";
};
/*
* The SoC is actually the 456MHz version, but because of the fixed regulator
* This is the fastest we can go.
*/
&opp_375 {
status = "okay";
};
&pmx_core {
status = "okay";

View File

@ -16,6 +16,56 @@
reg = <0xc0000000 0x0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu: cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
reg = <0>;
clocks = <&psc0 14>;
operating-points-v2 = <&opp_table>;
};
};
opp_table: opp-table {
compatible = "operating-points-v2";
opp_100: opp100-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <1000000 950000 1050000>;
};
opp_200: opp110-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1100000 1050000 1160000>;
};
opp_300: opp120-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1200000 1140000 1320000>;
};
/*
* Original silicon was 300MHz max, so higher frequencies
* need to be enabled on a per-board basis if the chip is
* capable.
*/
opp_375: opp120-375000000 {
status = "disabled";
opp-hz = /bits/ 64 <375000000>;
opp-microvolt = <1200000 1140000 1320000>;
};
opp_456: opp130-456000000 {
status = "disabled";
opp-hz = /bits/ 64 <456000000>;
opp-microvolt = <1300000 1250000 1350000>;
};
};
arm {
#address-cells = <1>;
#size-cells = <1>;

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@ -45,6 +45,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
CONFIG_CPUFREQ_DT=m
CONFIG_CPU_IDLE=y
CONFIG_NET=y
CONFIG_PACKET=y