This pull request adds CPUFreq support for DA850 boards in device-tree
boot using the generic CPUFREQ_DT driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJdC0qMAAoJEGFBu2jqvgRNSxMQAJHdPnwb6v4UOQBagv5T8mbz GbIwiQeIoc5/+z9zZ5+8Avrrbz32nLi/PE5Y3i+0sGxcGTTwbb2G7z43GloPlMHl YGyIfqzxuv4gM7FKaeWlSz7yNTrfWCaj5yTeLNQClYmV06sqXEDAL1OMn12BVAs4 MGaie45nf5WJda2FcXQyhuGMTs0WHoghxh2ajU19aVZGWOf3SEqej7Ot9FhwqXtT wuZ6X52JDLaAHKv0n/zFvF/YxyUxvFm6swPZ+Bq+6GBlxYxlTIruMwShLjUWh/J1 18ZuIgUG0Y1Tud3h44xnW3hWMY/jN4Pv+JmLdtJe8jO0l7taotxzHE2hck2FmnXV 5NFwlwqzODAmpAL2Jm/LpGQDc40XPg4IDdWvIk7tseiuoO1z1zswWnvmNu707+Ml 8kXjmk3X59Ms8rflc3rUr24no+K7vbiUEbJcPjr+EpB5KcKpLS7LHNhZRs1J4ilA TbfHMkbjHdO0wKUg+/sWdBRrLXR41uTsmpfkgvTNvOtdHq1AtgW3Jv2vHfQSyFXb cmN6SQIk8von0vjbIkdyWXSmOZln8ZpPpJO8cxXqzRqoopV/R4mxThEQ5uTfypNl +8Vp9p4zC0X6hdaXvgOQNdL3igFWcRXk8KEZOT5ddibWuXlXM6Siuy75tG4Y33j5 N04CB4BniX37bBPPFtVi =AF9Z -----END PGP SIGNATURE----- Merge tag 'davinci-for-v5.3/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into arm/dt This pull request adds CPUFreq support for DA850 boards in device-tree boot using the generic CPUFREQ_DT driver. * tag 'davinci-for-v5.3/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci_all_defconfig: Enable CPUFREQ_DT ARM: dts: da850-evm: enable cpufreq ARM: dts: da850-lcdk: enable cpufreq ARM: dts: da850-lego-ev3: enable cpufreq ARM: dts: da850: add cpu node and operating points to DT Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
19339e6a22
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@ -188,6 +188,19 @@
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};
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};
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&cpu {
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cpu-supply = <&vdcdc3_reg>;
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};
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/*
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* The standard da850-evm kits and SOM's are 375MHz so enable this operating
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* point by default. Higher frequencies must be enabled for custom boards with
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* other variants of the SoC.
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*/
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&opp_375 {
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status = "okay";
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};
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&sata {
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status = "okay";
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};
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@ -154,12 +154,48 @@
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};
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};
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};
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cvdd: regulator0 {
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compatible = "regulator-fixed";
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regulator-name = "cvdd";
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regulator-min-microvolt = <1300000>;
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regulator-max-microvolt = <1300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&ref_clk {
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clock-frequency = <24000000>;
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};
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&cpu {
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cpu-supply = <&cvdd>;
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};
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/*
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* LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are
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* valid. Unfortunately due to a problem with the DA8XX OHCI controller, we
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* can't enable more than one OPP by default, since the controller sometimes
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* becomes unresponsive after a transition. Fix the frequency at 456 MHz.
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*/
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&opp_100 {
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status = "disabled";
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};
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&opp_200 {
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status = "disabled";
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};
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&opp_300 {
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status = "disabled";
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};
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&opp_456 {
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status = "okay";
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};
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&pmx_core {
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status = "okay";
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@ -122,6 +122,15 @@
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amp-supply = <&>;
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};
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cvdd: regulator0 {
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compatible = "regulator-fixed";
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regulator-name = "cvdd";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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regulator-boot-on;
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};
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/*
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* This is a 5V current limiting regulator that is shared by USB,
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* the sensor (input) ports, the motor (output) ports and the A/DC.
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@ -201,6 +210,27 @@
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clock-frequency = <24000000>;
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};
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&cpu {
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cpu-supply = <&cvdd>;
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};
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/* since we have a fixed regulator, we can't run at these points */
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&opp_100 {
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status = "disabled";
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};
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&opp_200 {
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status = "disabled";
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};
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/*
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* The SoC is actually the 456MHz version, but because of the fixed regulator
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* This is the fastest we can go.
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*/
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&opp_375 {
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status = "okay";
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};
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&pmx_core {
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status = "okay";
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@ -16,6 +16,56 @@
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reg = <0xc0000000 0x0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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reg = <0>;
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clocks = <&psc0 14>;
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operating-points-v2 = <&opp_table>;
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};
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};
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opp_table: opp-table {
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compatible = "operating-points-v2";
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opp_100: opp100-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <1000000 950000 1050000>;
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};
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opp_200: opp110-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <1100000 1050000 1160000>;
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};
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opp_300: opp120-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <1200000 1140000 1320000>;
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};
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/*
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* Original silicon was 300MHz max, so higher frequencies
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* need to be enabled on a per-board basis if the chip is
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* capable.
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*/
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opp_375: opp120-375000000 {
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status = "disabled";
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opp-hz = /bits/ 64 <375000000>;
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opp-microvolt = <1200000 1140000 1320000>;
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};
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opp_456: opp130-456000000 {
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status = "disabled";
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opp-hz = /bits/ 64 <456000000>;
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opp-microvolt = <1300000 1250000 1350000>;
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};
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};
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arm {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -45,6 +45,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
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CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
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CONFIG_CPU_FREQ_GOV_POWERSAVE=m
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CONFIG_CPU_FREQ_GOV_ONDEMAND=m
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CONFIG_CPUFREQ_DT=m
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CONFIG_CPU_IDLE=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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