Merge series "ASoC: minor cleanup of warnings" from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:
Sparse, make W=1 and cppcheck all report minor warnings. The only functional change is in patch7 where the error code is now returned to the caller. Pierre-Louis Bossart (8): ASoC: topology: handle endianness warning ASoC: rt5682s: use 'static' qualifier ASoC: nau8821: fix kernel-doc ASoC: nau8821: clarify out-of-bounds check ASoC: mediatek: remove unnecessary initialization ASoC: mediatek: mt8195: rename shadowed array ASoC: mediatek: mt8195: fix return value ASoC: rockchip: i2s_tdm: improve return value handling sound/soc/codecs/nau8821.c | 6 ++++-- sound/soc/codecs/rt5682s.c | 6 +++--- sound/soc/mediatek/common/mtk-afe-fe-dai.c | 2 +- sound/soc/mediatek/mt8195/mt8195-afe-pcm.c | 4 ++-- sound/soc/mediatek/mt8195/mt8195-dai-etdm.c | 2 +- sound/soc/rockchip/rockchip_i2s_tdm.c | 2 +- sound/soc/soc-topology.c | 2 +- 7 files changed, 13 insertions(+), 11 deletions(-) -- 2.25.1
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commit
192cf41fef
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@ -381,7 +381,7 @@ static int dmic_clock_control(struct snd_soc_dapm_widget *w,
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speed_selection = dmic_speed_sel[i].val;
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break;
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}
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if (speed_selection < 0)
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if (i == 4)
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return -EINVAL;
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dev_dbg(nau8821->dev,
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@ -1178,7 +1178,9 @@ static void nau8821_fll_apply(struct nau8821 *nau8821,
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/**
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* nau8821_set_fll - FLL configuration of nau8821
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* @codec: codec component
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* @component: codec component
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* @pll_id: PLL requested
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* @source: clock source
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* @freq_in: frequency of input clock source
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* @freq_out: must be 256*Fs in order to achieve the best performance
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*
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@ -41,7 +41,7 @@ static const struct rt5682s_platform_data i2s_default_platform_data = {
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.dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk",
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};
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const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = {
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static const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = {
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"AVDD",
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"MICVDD",
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};
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@ -71,7 +71,7 @@ static void rt5682s_apply_patch_list(struct rt5682s_priv *rt5682s,
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dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
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}
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const struct reg_default rt5682s_reg[] = {
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static const struct reg_default rt5682s_reg[] = {
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{0x0002, 0x8080},
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{0x0003, 0x0001},
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{0x0005, 0x0000},
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@ -2838,7 +2838,7 @@ static int rt5682s_resume(struct snd_soc_component *component)
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#define rt5682s_resume NULL
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#endif
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const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = {
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static const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = {
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.hw_params = rt5682s_hw_params,
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.set_fmt = rt5682s_set_dai_fmt,
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.set_tdm_slot = rt5682s_set_tdm_slot,
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@ -350,7 +350,7 @@ int mtk_afe_resume(struct snd_soc_component *component)
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struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
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struct device *dev = afe->dev;
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struct regmap *regmap = afe->regmap;
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int i = 0;
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int i;
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if (pm_runtime_status_suspended(dev) || !afe->suspended)
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return 0;
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@ -2232,7 +2232,7 @@ static const struct mtk_base_memif_data memif_data[MT8195_AFE_MEMIF_NUM] = {
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},
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};
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static const struct mtk_base_irq_data irq_data[MT8195_AFE_IRQ_NUM] = {
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static const struct mtk_base_irq_data irq_data_array[MT8195_AFE_IRQ_NUM] = {
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[MT8195_AFE_IRQ_1] = {
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.id = MT8195_AFE_IRQ_1,
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.irq_cnt_reg = -1,
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@ -3100,7 +3100,7 @@ static int mt8195_afe_pcm_dev_probe(struct platform_device *pdev)
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return -ENOMEM;
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for (i = 0; i < afe->irqs_size; i++)
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afe->irqs[i].irq_data = &irq_data[i];
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afe->irqs[i].irq_data = &irq_data_array[i];
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/* init memif */
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afe->memif_size = MT8195_AFE_MEMIF_NUM;
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@ -1316,7 +1316,7 @@ static int mt8195_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id)
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}
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out:
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spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
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return 0;
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return ret;
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}
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static int etdm_cowork_slv_sel(int id, int slave_mode)
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@ -596,7 +596,7 @@ static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
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i2s_tdm->clk_ppm = ppm;
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return ret;
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return 0;
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}
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static int rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
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@ -1485,7 +1485,7 @@ static int soc_tplg_dapm_widget_create(struct soc_tplg *tplg,
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if (!kcontrol_type)
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goto err;
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for (i = 0; i < w->num_kcontrols; i++) {
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for (i = 0; i < le32_to_cpu(w->num_kcontrols); i++) {
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control_hdr = (struct snd_soc_tplg_ctl_hdr *)tplg->pos;
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switch (le32_to_cpu(control_hdr->ops.info)) {
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case SND_SOC_TPLG_CTL_VOLSW:
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