KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2 changes
So far we were flushing almost the entire universe whenever a VM would load/unload the SCTLR_EL1 and the two versions of that register had different MMU enabled settings. This turned out to be so slow that it prevented forward progress for a nested VM, because a scheduler timer tick interrupt would always be pending when we reached the nested VM. To avoid this problem, we consider the SCTLR_EL2 when evaluating if caches are on or off when entering virtual EL2 (because this is the value that we end up shadowing onto the hardware EL1 register). Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Jintack Lim <jintack.lim@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230209175820.1939006-19-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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@ -115,6 +115,7 @@ alternative_cb_end
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_host.h>
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void kvm_update_va_mask(struct alt_instr *alt,
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@ -192,7 +193,15 @@ struct kvm;
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static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
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{
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return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
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u64 cache_bits = SCTLR_ELx_M | SCTLR_ELx_C;
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int reg;
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if (vcpu_is_el2(vcpu))
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reg = SCTLR_EL2;
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else
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reg = SCTLR_EL1;
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return (vcpu_read_sys_reg(vcpu, reg) & cache_bits) == cache_bits;
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}
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static inline void __clean_dcache_guest_page(void *va, size_t size)
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