drm/radeon: enable SRBM timeout interrupt on SI
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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dc12a3ec71
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@ -3162,6 +3162,8 @@ static void si_gpu_init(struct radeon_device *rdev)
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}
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WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
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WREG32(SRBM_INT_CNTL, 1);
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WREG32(SRBM_INT_ACK, 1);
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evergreen_fix_pci_max_read_req_size(rdev);
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@ -5911,6 +5913,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
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tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
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WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
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WREG32(GRBM_INT_CNTL, 0);
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WREG32(SRBM_INT_CNTL, 0);
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if (rdev->num_crtc >= 2) {
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WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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@ -6610,6 +6613,10 @@ restart_ih:
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break;
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}
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break;
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case 96:
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DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
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WREG32(SRBM_INT_ACK, 0x1);
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break;
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case 124: /* UVD */
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DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
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radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
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@ -358,6 +358,10 @@
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#define CC_SYS_RB_BACKEND_DISABLE 0xe80
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#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
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#define SRBM_READ_ERROR 0xE98
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#define SRBM_INT_CNTL 0xEA0
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#define SRBM_INT_ACK 0xEA8
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#define SRBM_STATUS2 0x0EC4
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#define DMA_BUSY (1 << 5)
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#define DMA1_BUSY (1 << 6)
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