v4l: vsp1: Add support for multiple DRM pipelines
The R-Car H3 ES2.0 VSP-DL instance has two LIF entities and can drive two display pipelines at the same time. Refactor the VSP DRM code to support that by introducing a vsp_drm_pipeline object that models one display pipeline. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Acked-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
parent
3be0bf9734
commit
1837379e95
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@ -34,10 +34,10 @@
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static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe)
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{
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struct vsp1_drm *drm = to_vsp1_drm(pipe);
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struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
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if (drm->du_complete)
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drm->du_complete(drm->du_private);
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if (drm_pipe->du_complete)
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drm_pipe->du_complete(drm_pipe->du_private);
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}
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/* -----------------------------------------------------------------------------
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@ -80,15 +80,22 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
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const struct vsp1_du_lif_config *cfg)
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{
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struct vsp1_device *vsp1 = dev_get_drvdata(dev);
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struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
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struct vsp1_bru *bru = vsp1->bru;
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struct vsp1_drm_pipeline *drm_pipe;
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struct vsp1_pipeline *pipe;
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struct vsp1_bru *bru;
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struct v4l2_subdev_format format;
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const char *bru_name;
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unsigned int i;
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int ret;
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if (pipe_index > 0)
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if (pipe_index >= vsp1->info->lif_count)
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return -EINVAL;
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drm_pipe = &vsp1->drm->pipe[pipe_index];
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pipe = &drm_pipe->pipe;
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bru = to_bru(&pipe->bru->subdev);
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bru_name = pipe->bru->type == VSP1_ENTITY_BRU ? "BRU" : "BRS";
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if (!cfg) {
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/*
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* NULL configuration means the CRTC is being disabled, stop
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@ -100,14 +107,25 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
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media_pipeline_stop(&pipe->output->entity.subdev.entity);
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for (i = 0; i < bru->entity.source_pad; ++i) {
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vsp1->drm->inputs[i].enabled = false;
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bru->inputs[i].rpf = NULL;
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for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
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struct vsp1_rwpf *rpf = pipe->inputs[i];
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if (!rpf)
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continue;
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/*
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* Remove the RPF from the pipe and the list of BRU
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* inputs.
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*/
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WARN_ON(list_empty(&rpf->entity.list_pipe));
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list_del_init(&rpf->entity.list_pipe);
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pipe->inputs[i] = NULL;
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bru->inputs[rpf->bru_input].rpf = NULL;
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}
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drm_pipe->du_complete = NULL;
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pipe->num_inputs = 0;
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vsp1->drm->du_complete = NULL;
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vsp1_dlm_reset(pipe->output->dlm);
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vsp1_device_put(vsp1);
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@ -117,8 +135,8 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
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return 0;
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}
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dev_dbg(vsp1->dev, "%s: configuring LIF with format %ux%u\n",
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__func__, cfg->width, cfg->height);
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dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u\n",
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__func__, pipe_index, cfg->width, cfg->height);
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/*
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* Configure the format at the BRU sinks and propagate it through the
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@ -127,7 +145,7 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
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memset(&format, 0, sizeof(format));
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format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
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for (i = 0; i < bru->entity.source_pad; ++i) {
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for (i = 0; i < pipe->bru->source_pad; ++i) {
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format.pad = i;
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format.format.width = cfg->width;
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@ -135,60 +153,60 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
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format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
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format.format.field = V4L2_FIELD_NONE;
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ret = v4l2_subdev_call(&bru->entity.subdev, pad,
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ret = v4l2_subdev_call(&pipe->bru->subdev, pad,
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set_fmt, NULL, &format);
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if (ret < 0)
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return ret;
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dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n",
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dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
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__func__, format.format.width, format.format.height,
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format.format.code, i);
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format.format.code, bru_name, i);
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}
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format.pad = bru->entity.source_pad;
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format.pad = pipe->bru->source_pad;
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format.format.width = cfg->width;
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format.format.height = cfg->height;
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format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
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format.format.field = V4L2_FIELD_NONE;
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ret = v4l2_subdev_call(&bru->entity.subdev, pad, set_fmt, NULL,
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ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_fmt, NULL,
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&format);
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if (ret < 0)
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return ret;
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dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n",
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dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
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__func__, format.format.width, format.format.height,
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format.format.code, i);
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format.format.code, bru_name, i);
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format.pad = RWPF_PAD_SINK;
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ret = v4l2_subdev_call(&vsp1->wpf[0]->entity.subdev, pad, set_fmt, NULL,
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ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
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&format);
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if (ret < 0)
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return ret;
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dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF0 sink\n",
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dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
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__func__, format.format.width, format.format.height,
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format.format.code);
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format.format.code, pipe->output->entity.index);
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format.pad = RWPF_PAD_SOURCE;
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ret = v4l2_subdev_call(&vsp1->wpf[0]->entity.subdev, pad, get_fmt, NULL,
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ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
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&format);
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if (ret < 0)
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return ret;
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dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF0 source\n",
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dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",
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__func__, format.format.width, format.format.height,
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format.format.code);
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format.format.code, pipe->output->entity.index);
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format.pad = LIF_PAD_SINK;
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ret = v4l2_subdev_call(&vsp1->lif[0]->entity.subdev, pad, set_fmt, NULL,
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ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
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&format);
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if (ret < 0)
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return ret;
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dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF sink\n",
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dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",
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__func__, format.format.width, format.format.height,
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format.format.code);
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format.format.code, pipe_index);
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/*
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* Verify that the format at the output of the pipeline matches the
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@ -216,8 +234,8 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
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* Register a callback to allow us to notify the DRM driver of frame
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* completion events.
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*/
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vsp1->drm->du_complete = cfg->callback;
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vsp1->drm->du_private = cfg->callback_data;
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drm_pipe->du_complete = cfg->callback;
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drm_pipe->du_private = cfg->callback_data;
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ret = media_pipeline_start(&pipe->output->entity.subdev.entity,
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&pipe->pipe);
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@ -245,9 +263,9 @@ EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
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void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
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{
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struct vsp1_device *vsp1 = dev_get_drvdata(dev);
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struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
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struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
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vsp1->drm->num_inputs = pipe->num_inputs;
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drm_pipe->enabled = drm_pipe->pipe.num_inputs != 0;
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}
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EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
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@ -286,6 +304,7 @@ int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
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const struct vsp1_du_atomic_config *cfg)
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{
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struct vsp1_device *vsp1 = dev_get_drvdata(dev);
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struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
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const struct vsp1_format_info *fmtinfo;
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struct vsp1_rwpf *rpf;
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@ -298,7 +317,12 @@ int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
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dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__,
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rpf_index);
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vsp1->drm->inputs[rpf_index].enabled = false;
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/*
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* Remove the RPF from the pipe's inputs. The atomic flush
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* handler will disable the input and remove the entity from the
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* pipe's entities list.
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*/
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drm_pipe->pipe.inputs[rpf_index] = NULL;
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return 0;
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}
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vsp1->drm->inputs[rpf_index].crop = cfg->src;
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vsp1->drm->inputs[rpf_index].compose = cfg->dst;
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vsp1->drm->inputs[rpf_index].zpos = cfg->zpos;
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vsp1->drm->inputs[rpf_index].enabled = true;
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drm_pipe->pipe.inputs[rpf_index] = rpf;
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return 0;
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}
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EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);
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static int vsp1_du_setup_rpf_pipe(struct vsp1_device *vsp1,
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struct vsp1_pipeline *pipe,
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struct vsp1_rwpf *rpf, unsigned int bru_input)
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{
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struct v4l2_subdev_selection sel;
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/* BRU sink, propagate the format from the RPF source. */
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format.pad = bru_input;
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ret = v4l2_subdev_call(&vsp1->bru->entity.subdev, pad, set_fmt, NULL,
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ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_fmt, NULL,
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&format);
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if (ret < 0)
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return ret;
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sel.target = V4L2_SEL_TGT_COMPOSE;
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sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
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ret = v4l2_subdev_call(&vsp1->bru->entity.subdev, pad, set_selection,
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NULL, &sel);
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ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_selection, NULL,
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&sel);
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if (ret < 0)
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return ret;
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@ -453,14 +479,20 @@ static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
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void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
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{
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struct vsp1_device *vsp1 = dev_get_drvdata(dev);
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struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
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struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
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struct vsp1_pipeline *pipe = &drm_pipe->pipe;
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struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
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struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
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struct vsp1_entity *entity;
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struct vsp1_entity *next;
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struct vsp1_dl_list *dl;
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const char *bru_name;
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unsigned long flags;
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unsigned int i;
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int ret;
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bru_name = pipe->bru->type == VSP1_ENTITY_BRU ? "BRU" : "BRS";
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/* Prepare the display list. */
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dl = vsp1_dl_list_get(pipe->output->dlm);
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struct vsp1_rwpf *rpf = vsp1->rpf[i];
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unsigned int j;
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if (!vsp1->drm->inputs[i].enabled) {
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pipe->inputs[i] = NULL;
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if (!pipe->inputs[i])
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continue;
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}
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pipe->inputs[i] = rpf;
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/* Insert the RPF in the sorted RPFs array. */
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for (j = pipe->num_inputs++; j > 0; --j) {
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}
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/* Setup the RPF input pipeline for every enabled input. */
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for (i = 0; i < vsp1->info->num_bru_inputs; ++i) {
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for (i = 0; i < pipe->bru->source_pad; ++i) {
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struct vsp1_rwpf *rpf = inputs[i];
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if (!rpf) {
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vsp1->bru->inputs[i].rpf = NULL;
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bru->inputs[i].rpf = NULL;
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continue;
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}
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vsp1->bru->inputs[i].rpf = rpf;
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if (list_empty(&rpf->entity.list_pipe))
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list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
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bru->inputs[i].rpf = rpf;
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rpf->bru_input = i;
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rpf->entity.sink = &vsp1->bru->entity;
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rpf->entity.sink = pipe->bru;
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rpf->entity.sink_pad = i;
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dev_dbg(vsp1->dev, "%s: connecting RPF.%u to BRU:%u\n",
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__func__, rpf->entity.index, i);
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dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
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__func__, rpf->entity.index, bru_name, i);
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ret = vsp1_du_setup_rpf_pipe(vsp1, rpf, i);
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ret = vsp1_du_setup_rpf_pipe(vsp1, pipe, rpf, i);
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if (ret < 0)
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dev_err(vsp1->dev,
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"%s: failed to setup RPF.%u\n",
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@ -513,16 +544,16 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
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}
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/* Configure all entities in the pipeline. */
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list_for_each_entry(entity, &pipe->entities, list_pipe) {
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list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
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/* Disconnect unused RPFs from the pipeline. */
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if (entity->type == VSP1_ENTITY_RPF) {
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struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev);
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if (entity->type == VSP1_ENTITY_RPF &&
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!pipe->inputs[entity->index]) {
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vsp1_dl_list_write(dl, entity->route->reg,
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VI6_DPR_NODE_UNUSED);
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if (!pipe->inputs[rpf->entity.index]) {
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vsp1_dl_list_write(dl, entity->route->reg,
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VI6_DPR_NODE_UNUSED);
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continue;
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}
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list_del_init(&entity->list_pipe);
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continue;
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}
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vsp1_entity_route_setup(entity, pipe, dl);
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@ -540,11 +571,11 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
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vsp1_dl_list_commit(dl);
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/* Start or stop the pipeline if needed. */
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if (!vsp1->drm->num_inputs && pipe->num_inputs) {
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if (!drm_pipe->enabled && pipe->num_inputs) {
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spin_lock_irqsave(&pipe->irqlock, flags);
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vsp1_pipeline_run(pipe);
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spin_unlock_irqrestore(&pipe->irqlock, flags);
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} else if (vsp1->drm->num_inputs && !pipe->num_inputs) {
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} else if (drm_pipe->enabled && !pipe->num_inputs) {
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vsp1_pipeline_stop(pipe);
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}
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}
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@ -579,39 +610,46 @@ EXPORT_SYMBOL_GPL(vsp1_du_unmap_sg);
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int vsp1_drm_init(struct vsp1_device *vsp1)
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{
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struct vsp1_pipeline *pipe;
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unsigned int i;
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vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);
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if (!vsp1->drm)
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return -ENOMEM;
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pipe = &vsp1->drm->pipe;
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/* Create one DRM pipeline per LIF. */
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for (i = 0; i < vsp1->info->lif_count; ++i) {
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struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];
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struct vsp1_pipeline *pipe = &drm_pipe->pipe;
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vsp1_pipeline_init(pipe);
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vsp1_pipeline_init(pipe);
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/* The DRM pipeline is static, add entities manually. */
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/*
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* The DRM pipeline is static, add entities manually. The first
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* pipeline uses the BRU and the second pipeline the BRS.
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*/
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pipe->bru = i == 0 ? &vsp1->bru->entity : &vsp1->brs->entity;
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pipe->lif = &vsp1->lif[i]->entity;
|
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pipe->output = vsp1->wpf[i];
|
||||
pipe->output->pipe = pipe;
|
||||
pipe->frame_end = vsp1_du_pipeline_frame_end;
|
||||
|
||||
pipe->bru->sink = &pipe->output->entity;
|
||||
pipe->bru->sink_pad = 0;
|
||||
pipe->output->entity.sink = pipe->lif;
|
||||
pipe->output->entity.sink_pad = 0;
|
||||
|
||||
list_add_tail(&pipe->bru->list_pipe, &pipe->entities);
|
||||
list_add_tail(&pipe->lif->list_pipe, &pipe->entities);
|
||||
list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
|
||||
}
|
||||
|
||||
/* Disable all RPFs initially. */
|
||||
for (i = 0; i < vsp1->info->rpf_count; ++i) {
|
||||
struct vsp1_rwpf *input = vsp1->rpf[i];
|
||||
|
||||
list_add_tail(&input->entity.list_pipe, &pipe->entities);
|
||||
INIT_LIST_HEAD(&input->entity.list_pipe);
|
||||
}
|
||||
|
||||
vsp1->bru->entity.sink = &vsp1->wpf[0]->entity;
|
||||
vsp1->bru->entity.sink_pad = 0;
|
||||
vsp1->wpf[0]->entity.sink = &vsp1->lif[0]->entity;
|
||||
vsp1->wpf[0]->entity.sink_pad = 0;
|
||||
|
||||
list_add_tail(&vsp1->bru->entity.list_pipe, &pipe->entities);
|
||||
list_add_tail(&vsp1->wpf[0]->entity.list_pipe, &pipe->entities);
|
||||
list_add_tail(&vsp1->lif[0]->entity.list_pipe, &pipe->entities);
|
||||
|
||||
pipe->bru = &vsp1->bru->entity;
|
||||
pipe->lif = &vsp1->lif[0]->entity;
|
||||
pipe->output = vsp1->wpf[0];
|
||||
pipe->output->pipe = pipe;
|
||||
pipe->frame_end = vsp1_du_pipeline_frame_end;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -18,32 +18,41 @@
|
|||
#include "vsp1_pipe.h"
|
||||
|
||||
/**
|
||||
* vsp1_drm - State for the API exposed to the DRM driver
|
||||
* vsp1_drm_pipeline - State for the API exposed to the DRM driver
|
||||
* @pipe: the VSP1 pipeline used for display
|
||||
* @num_inputs: number of active pipeline inputs at the beginning of an update
|
||||
* @inputs: source crop rectangle, destination compose rectangle and z-order
|
||||
* position for every input
|
||||
* @enabled: pipeline state at the beginning of an update
|
||||
* @du_complete: frame completion callback for the DU driver (optional)
|
||||
* @du_private: data to be passed to the du_complete callback
|
||||
*/
|
||||
struct vsp1_drm {
|
||||
struct vsp1_drm_pipeline {
|
||||
struct vsp1_pipeline pipe;
|
||||
unsigned int num_inputs;
|
||||
struct {
|
||||
bool enabled;
|
||||
struct v4l2_rect crop;
|
||||
struct v4l2_rect compose;
|
||||
unsigned int zpos;
|
||||
} inputs[VSP1_MAX_RPF];
|
||||
bool enabled;
|
||||
|
||||
/* Frame synchronisation */
|
||||
void (*du_complete)(void *);
|
||||
void *du_private;
|
||||
};
|
||||
|
||||
static inline struct vsp1_drm *to_vsp1_drm(struct vsp1_pipeline *pipe)
|
||||
/**
|
||||
* vsp1_drm - State for the API exposed to the DRM driver
|
||||
* @pipe: the VSP1 DRM pipeline used for display
|
||||
* @inputs: source crop rectangle, destination compose rectangle and z-order
|
||||
* position for every input (indexed by RPF index)
|
||||
*/
|
||||
struct vsp1_drm {
|
||||
struct vsp1_drm_pipeline pipe[VSP1_MAX_LIF];
|
||||
|
||||
struct {
|
||||
struct v4l2_rect crop;
|
||||
struct v4l2_rect compose;
|
||||
unsigned int zpos;
|
||||
} inputs[VSP1_MAX_RPF];
|
||||
};
|
||||
|
||||
static inline struct vsp1_drm_pipeline *
|
||||
to_vsp1_drm_pipeline(struct vsp1_pipeline *pipe)
|
||||
{
|
||||
return container_of(pipe, struct vsp1_drm, pipe);
|
||||
return container_of(pipe, struct vsp1_drm_pipeline, pipe);
|
||||
}
|
||||
|
||||
int vsp1_drm_init(struct vsp1_device *vsp1);
|
||||
|
|
Loading…
Reference in New Issue