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drm/i915: Don't apply the 16Gb DIMM wm latency w/a to BXT/GLK 

The 16Gb DIMM w/a is not applicable to BXT or GLK. Limit it to
the appropriate platforms.

This was especially harsh on GLK since we don't even try to read
the DIMM information on that platforms, hence valid_dimm was
always false and thus we always tried to apply the w/a.
Furthermore the w/a pushed the level 0 latency above the
level 1 latency, which doesn't really make sense.

v2: Do the check when populating is_16gb_dimm (Mahesh)

Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Fixes: 86b592876c ("drm/i915: Implement 16GB dimm wa for latency level-0")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181023182102.31549-1-ville.syrjala@linux.intel.com
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mahesh Kumar <mahesh1.sh.kumar@gmail.com>
(cherry picked from commit 5d6f36b27d)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
Ville Syrjälä 2018-10-23 21:21:02 +03:00 committed by Joonas Lahtinen
parent 651022382c
commit 18354b422c
3 changed files with 9 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/drm/i915/i915_drv.c
View File

@ -1175,8 +1175,6 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
return -EINVAL; return -EINVAL;
} }
dram_info->valid_dimm = true;
/* /*
* If any of the channel is single rank channel, worst case output * If any of the channel is single rank channel, worst case output
* will be same as if single rank memory, so consider single rank * will be same as if single rank memory, so consider single rank
@ -1193,8 +1191,7 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
return -EINVAL; return -EINVAL;
} }
if (ch0.is_16gb_dimm || ch1.is_16gb_dimm) dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
dram_info->is_16gb_dimm = true;
dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0, dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
val_ch1, val_ch1,
@ -1314,7 +1311,6 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
return -EINVAL; return -EINVAL;
} }
dram_info->valid_dimm = true;
dram_info->valid = true; dram_info->valid = true;
return 0; return 0;
} }
@ -1327,12 +1323,17 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
int ret; int ret;
dram_info->valid = false; dram_info->valid = false;
dram_info->valid_dimm = false;
dram_info->is_16gb_dimm = false;
dram_info->rank = I915_DRAM_RANK_INVALID; dram_info->rank = I915_DRAM_RANK_INVALID;
dram_info->bandwidth_kbps = 0; dram_info->bandwidth_kbps = 0;
dram_info->num_channels = 0; dram_info->num_channels = 0;
/*
* Assume 16Gb DIMMs are present until proven otherwise.
* This is only used for the level 0 watermark latency
* w/a which does not apply to bxt/glk.
*/
dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv)) if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
return; return;

1
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1948,7 +1948,6 @@ struct drm_i915_private {
struct dram_info { struct dram_info {
bool valid; bool valid;
bool valid_dimm;
bool is_16gb_dimm; bool is_16gb_dimm;
u8 num_channels; u8 num_channels;
enum dram_rank { enum dram_rank {

3
drivers/gpu/drm/i915/intel_pm.c
View File

@ -2881,8 +2881,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
* any underrun. If not able to get Dimm info assume 16GB dimm * any underrun. If not able to get Dimm info assume 16GB dimm
* to avoid any underrun. * to avoid any underrun.
*/ */
if (!dev_priv->dram_info.valid_dimm || if (dev_priv->dram_info.is_16gb_dimm)
dev_priv->dram_info.is_16gb_dimm)
wm[0] += 1; wm[0] += 1;
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {