drm/i915: gen6_enable_rps() wants to be called after ring initialisation
Currently we call gen6_enable_rps() (which writes into the per-ring register mmio space) from intel_modeset_init_hw() which is called before we initialise the rings. If we defer intel_modeset_init_hw() until afterwards (in the intel_modeset_gem_init() phase) all is well. v2: Rectify ordering of gem vs display HW init upon resume. (Daniel) v3: Fix up locking. (Paulo) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Smash Paulo's locking fix onto Chris' patch.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -624,15 +624,16 @@ static int i915_drm_thaw(struct drm_device *dev)
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/* KMS EnterVT equivalent */
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if (drm_core_check_feature(dev, DRIVER_MODESET)) {
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if (HAS_PCH_SPLIT(dev))
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ironlake_init_pch_refclk(dev);
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mutex_lock(&dev->struct_mutex);
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dev_priv->mm.suspended = 0;
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error = i915_gem_init_hw(dev);
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mutex_unlock(&dev->struct_mutex);
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if (HAS_PCH_SPLIT(dev))
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ironlake_init_pch_refclk(dev);
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intel_modeset_init_hw(dev);
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drm_mode_config_reset(dev);
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drm_irq_install(dev);
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@ -640,9 +641,6 @@ static int i915_drm_thaw(struct drm_device *dev)
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mutex_lock(&dev->mode_config.mutex);
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drm_helper_resume_force_mode(dev);
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mutex_unlock(&dev->mode_config.mutex);
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if (IS_IRONLAKE_M(dev))
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ironlake_enable_rc6(dev);
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}
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intel_opregion_init(dev);
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@ -876,12 +876,6 @@ int i915_restore_state(struct drm_device *dev)
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I915_WRITE(IER, dev_priv->saveIER);
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I915_WRITE(IMR, dev_priv->saveIMR);
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}
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mutex_unlock(&dev->struct_mutex);
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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intel_modeset_init_hw(dev);
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mutex_lock(&dev->struct_mutex);
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/* Cache mode state */
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I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
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@ -6658,6 +6658,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
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if (IS_IRONLAKE_M(dev)) {
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ironlake_enable_drps(dev);
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ironlake_enable_rc6(dev);
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intel_init_emon(dev);
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}
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@ -6719,8 +6720,6 @@ void intel_modeset_init(struct drm_device *dev)
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i915_disable_vga(dev);
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intel_setup_outputs(dev);
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intel_modeset_init_hw(dev);
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INIT_WORK(&dev_priv->idle_work, intel_idle_update);
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setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
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(unsigned long)dev);
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@ -6728,8 +6727,7 @@ void intel_modeset_init(struct drm_device *dev)
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void intel_modeset_gem_init(struct drm_device *dev)
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{
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if (IS_IRONLAKE_M(dev))
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ironlake_enable_rc6(dev);
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intel_modeset_init_hw(dev);
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intel_setup_overlay(dev);
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}
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