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rsi: reset device changes for 9116 

Device reset register(watchdog timer related) addresses and
values are different for 9116.

Signed-off-by: Siva Rebbagondla <siva8118@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Siva Rebbagondla 2019-04-03 09:43:08 +05:30 committed by Kalle Valo
parent 1533f976c6
commit 17ff2c794f
3 changed files with 91 additions and 30 deletions
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45
drivers/net/wireless/rsi/rsi_91x_sdio.c
View File

@ -1167,16 +1167,41 @@ static void rsi_reset_chip(struct rsi_hw *adapter)
* and any pending dma transfers to rf spi in device to finish.
*/
msleep(100);
ulp_read_write(adapter, RSI_ULP_RESET_REG, RSI_ULP_WRITE_0, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_1, RSI_ULP_WRITE_2, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_2, RSI_ULP_WRITE_0, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_1, RSI_ULP_WRITE_50,
32);
ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_2, RSI_ULP_WRITE_0,
32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_ENABLE,
RSI_ULP_TIMER_ENABLE, 32);
if (adapter->device_model != RSI_DEV_9116) {
ulp_read_write(adapter, RSI_ULP_RESET_REG, RSI_ULP_WRITE_0, 32);
ulp_read_write(adapter,
RSI_WATCH_DOG_TIMER_1, RSI_ULP_WRITE_2, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_2, RSI_ULP_WRITE_0,
32);
ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_1,
RSI_ULP_WRITE_50, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_2,
RSI_ULP_WRITE_0, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_ENABLE,
RSI_ULP_TIMER_ENABLE, 32);
} else {
if ((rsi_sdio_master_reg_write(adapter,
NWP_WWD_INTERRUPT_TIMER,
NWP_WWD_INT_TIMER_CLKS,
RSI_9116_REG_SIZE)) < 0) {
rsi_dbg(ERR_ZONE, "Failed to write to intr timer\n");
}
if ((rsi_sdio_master_reg_write(adapter,
NWP_WWD_SYSTEM_RESET_TIMER,
NWP_WWD_SYS_RESET_TIMER_CLKS,
RSI_9116_REG_SIZE)) < 0) {
rsi_dbg(ERR_ZONE,
"Failed to write to system reset timer\n");
}
if ((rsi_sdio_master_reg_write(adapter,
NWP_WWD_MODE_AND_RSTART,
NWP_WWD_TIMER_DISABLE,
RSI_9116_REG_SIZE)) < 0) {
rsi_dbg(ERR_ZONE,
"Failed to write to mode and restart\n");
}
rsi_dbg(ERR_ZONE, "***** Watch Dog Reset Successful *****\n");
}
/* This msleep will be sufficient for the ulp
* read write operations to complete for chip reset.
*/

61
drivers/net/wireless/rsi/rsi_91x_usb.c
View File

@ -698,26 +698,47 @@ static int rsi_reset_card(struct rsi_hw *adapter)
goto fail;
}
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_1,
RSI_ULP_WRITE_2, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_2,
RSI_ULP_WRITE_0, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_1,
RSI_ULP_WRITE_50, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_2,
RSI_ULP_WRITE_0, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_ENABLE,
RSI_ULP_TIMER_ENABLE, 32);
if (ret < 0)
goto fail;
if (adapter->device_model != RSI_DEV_9116) {
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_1,
RSI_ULP_WRITE_2, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_2,
RSI_ULP_WRITE_0, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_1,
RSI_ULP_WRITE_50, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_2,
RSI_ULP_WRITE_0, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_ENABLE,
RSI_ULP_TIMER_ENABLE, 32);
if (ret < 0)
goto fail;
} else {
if ((rsi_usb_master_reg_write(adapter,
NWP_WWD_INTERRUPT_TIMER,
NWP_WWD_INT_TIMER_CLKS,
RSI_9116_REG_SIZE)) < 0) {
goto fail;
}
if ((rsi_usb_master_reg_write(adapter,
NWP_WWD_SYSTEM_RESET_TIMER,
NWP_WWD_SYS_RESET_TIMER_CLKS,
RSI_9116_REG_SIZE)) < 0) {
goto fail;
}
if ((rsi_usb_master_reg_write(adapter,
NWP_WWD_MODE_AND_RSTART,
NWP_WWD_TIMER_DISABLE,
RSI_9116_REG_SIZE)) < 0) {
goto fail;
}
}
rsi_dbg(INFO_ZONE, "Reset card done\n");
return ret;

15
drivers/net/wireless/rsi/rsi_hal.h
View File

@ -70,6 +70,21 @@
#define RSI_WATCH_DOG_DELAY_TIMER_2 0x16f
#define RSI_WATCH_DOG_TIMER_ENABLE 0x170
/* Watchdog timer addresses for 9116 */
#define NWP_AHB_BASE_ADDR 0x41300000
#define NWP_WWD_INTERRUPT_TIMER (NWP_AHB_BASE_ADDR + 0x300)
#define NWP_WWD_SYSTEM_RESET_TIMER (NWP_AHB_BASE_ADDR + 0x304)
#define NWP_WWD_WINDOW_TIMER (NWP_AHB_BASE_ADDR + 0x308)
#define NWP_WWD_TIMER_SETTINGS (NWP_AHB_BASE_ADDR + 0x30C)
#define NWP_WWD_MODE_AND_RSTART (NWP_AHB_BASE_ADDR + 0x310)
#define NWP_WWD_RESET_BYPASS (NWP_AHB_BASE_ADDR + 0x314)
#define NWP_FSM_INTR_MASK_REG (NWP_AHB_BASE_ADDR + 0x104)
/* Watchdog timer values */
#define NWP_WWD_INT_TIMER_CLKS 5
#define NWP_WWD_SYS_RESET_TIMER_CLKS 4
#define NWP_WWD_TIMER_DISABLE 0xAA0001
#define RSI_ULP_WRITE_0 00
#define RSI_ULP_WRITE_2 02
#define RSI_ULP_WRITE_50 50