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e1000e: disable gig speed when in S0->Sx transition 

Most of this workaround is necessary for all ICHx/PCH parts so one of
the two MAC-type checks can be removed.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Bruce Allan 2010-06-17 18:59:48 +00:00 committed by David S. Miller
parent dbcb9fec5c
commit 17f085df92
1 changed files with 5 additions and 14 deletions
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19
drivers/net/e1000e/ich8lan.c
View File

@ -3457,21 +3457,12 @@ void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
{ {
u32 phy_ctrl; u32 phy_ctrl;
switch (hw->mac.type) { phy_ctrl = er32(PHY_CTRL);
case e1000_ich8lan: phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
case e1000_ich9lan: ew32(PHY_CTRL, phy_ctrl);
case e1000_ich10lan:
case e1000_pchlan:
phy_ctrl = er32(PHY_CTRL);
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
E1000_PHY_CTRL_GBE_DISABLE;
ew32(PHY_CTRL, phy_ctrl);
if (hw->mac.type == e1000_pchlan) if (hw->mac.type >= e1000_pchlan)
e1000_phy_hw_reset_ich8lan(hw); e1000_phy_hw_reset_ich8lan(hw);
default:
break;
}
} }
/** /**