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Renesas DTS updates for v6.4 (take two) 

- Add PWM support for the R-Car H1 and H2 SoCs,
   - Add slide switch and I2C support for the Marzen development board,
   - Add SCI (serial) and Camera support for the RZ/G2L SoC and the
     RZ/G2L SMARC EVK development board,
   - Add IOMMU support for the R-Car V4H SoC,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.4 (take two)

  - Add PWM support for the R-Car H1 and H2 SoCs,
  - Add slide switch and I2C support for the Marzen development board,
  - Add SCI (serial) and Camera support for the RZ/G2L SoC and the
    RZ/G2L SMARC EVK development board,
  - Add IOMMU support for the R-Car V4H SoC,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r8a779a0: Revise renesas,ipmmu-main
  arm64: dts: renesas: falcon-csi-dsi: Set bus-type for MAX96712
  arm64: dts: renesas: r8a779g0: Add iommus to MMC node
  arm64: dts: renesas: r8a779g0: Add iommus to DMAC nodes
  arm64: dts: renesas: r8a779g0: Add IPMMU nodes
  arm64: dts: renesas: r8a779f0: Revise renesas,ipmmu-main
  arm64: dts: renesas: rzg2l-smarc: Enable CRU, CSI support
  arm64: dts: renesas: r9a07g044: Add CSI and CRU nodes
  arm64: dts: renesas: r9a07g044: Enable SCI0 using DT overlay
  ARM: dts: r8a7790: Add PWM device nodes
  ARM: dts: r8a7790: Add TPU device node
  ARM: dts: marzen: Enable I2C support
  ARM: dts: marzen: Add slide switches
  ARM: dts: r8a7779: Add PWM support
  dt-bindings: clock: r8a7779: Add PWM module clock
  arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes

Link: https://lore.kernel.org/r/cover.1681113117.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-04-14 17:47:46 +02:00
parent 2925732f0c 2f04079bf5
commit 17e26de12a
15 changed files with 608 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

69
arch/arm/boot/dts/r8a7779-marzen.dts
View File

@ -9,6 +9,7 @@
/dts-v1/;
#include "r8a7779.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@ -66,6 +67,51 @@
vdd33a-supply = <&fixedregulator3v3>;
};
keyboard-irq {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_irq_pins>;
pinctrl-names = "default";
interrupt-parent = <&gpio0>;
key-1 {
interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
linux,code = <KEY_1>;
label = "SW1-1";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
linux,code = <KEY_2>;
label = "SW1-2";
wakeup-source;
debounce-interval = <20>;
};
};
keyboard-gpio {
compatible = "gpio-keys-polled";
poll-interval = <50>;
pinctrl-0 = <&keyboard_gpio_pins>;
pinctrl-names = "default";
key-3 {
gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW1-3";
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "SW1-4";
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
led2 {
@ -161,6 +207,20 @@
};
};
&gpio0 {
keyboard-irq-hog {
gpio-hog;
gpios = <17 GPIO_ACTIVE_LOW>, <18 GPIO_ACTIVE_LOW>;
input;
};
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
};
&irqpin0 {
status = "okay";
};
@ -223,6 +283,15 @@
groups = "hspi0";
function = "hspi0";
};
keyboard_irq_pins: keyboard-irq {
pins = "GP_0_17", "GP_0_18";
bias-pull-up;
};
keyboard_gpio_pins: keyboard-gpio {
pins = "GP_0_19", "GP_0_20";
bias-pull-up;
};
};
&sata {

91
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -324,6 +324,69 @@
status = "disabled";
};
pwm0: pwm@ffe50000 {
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
reg = <0xffe50000 0x8>;
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#pwm-cells = <2>;
status = "disabled";
};
pwm1: pwm@ffe51000 {
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
reg = <0xffe51000 0x8>;
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#pwm-cells = <2>;
status = "disabled";
};
pwm2: pwm@ffe52000 {
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
reg = <0xffe52000 0x8>;
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#pwm-cells = <2>;
status = "disabled";
};
pwm3: pwm@ffe53000 {
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
reg = <0xffe53000 0x8>;
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#pwm-cells = <2>;
status = "disabled";
};
pwm4: pwm@ffe54000 {
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
reg = <0xffe54000 0x8>;
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#pwm-cells = <2>;
status = "disabled";
};
pwm5: pwm@ffe55000 {
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
reg = <0xffe55000 0x8>;
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#pwm-cells = <2>;
status = "disabled";
};
pwm6: pwm@ffe56000 {
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
reg = <0xffe56000 0x8>;
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#pwm-cells = <2>;
status = "disabled";
};
pfc: pinctrl@fffc0000 {
compatible = "renesas,pfc-r8a7779";
reg = <0xfffc0000 0x23c>;
@ -554,7 +617,8 @@
compatible = "renesas,r8a7779-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0xffc80030 4>;
clocks = <&cpg_clocks R8A7779_CLK_S>,
clocks = <&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
@ -572,20 +636,21 @@
<&cpg_clocks R8A7779_CLK_P>;
#clock-cells = <1>;
clock-indices = <
R8A7779_CLK_HSPI R8A7779_CLK_TMU2
R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
R8A7779_CLK_PWM R8A7779_CLK_HSPI
R8A7779_CLK_TMU2 R8A7779_CLK_TMU1
R8A7779_CLK_TMU0 R8A7779_CLK_HSCIF1
R8A7779_CLK_HSCIF0 R8A7779_CLK_SCIF5
R8A7779_CLK_SCIF4 R8A7779_CLK_SCIF3
R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3
R8A7779_CLK_I2C2 R8A7779_CLK_I2C1
R8A7779_CLK_I2C0
>;
clock-output-names =
"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
"hscif0", "scif5", "scif4", "scif3", "scif2",
"scif1", "scif0", "i2c3", "i2c2", "i2c1",
"i2c0";
"pwm", "hspi", "tmu2", "tmu1", "tmu0",
"hscif1", "hscif0", "scif5", "scif4", "scif3",
"scif2", "scif1", "scif0", "i2c3", "i2c2",
"i2c1", "i2c0";
};
mstp1_clks: clocks@ffc80034 {
compatible = "renesas,r8a7779-mstp-clocks",

81
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -376,6 +376,17 @@
reg = <0 0xe6060000 0 0x250>;
};
tpu: pwm@e60f0000 {
compatible = "renesas,tpu-r8a7790", "renesas,tpu";
reg = <0 0xe60f0000 0 0x148>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 304>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 304>;
#pwm-cells = <3>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7790-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@ -1037,6 +1048,76 @@
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm4: pwm@e6e34000 {
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
reg = <0 0xe6e34000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm5: pwm@e6e35000 {
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
reg = <0 0xe6e35000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm6: pwm@e6e36000 {
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
reg = <0 0xe6e36000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
can0: can@e6e80000 {
compatible = "renesas,can-r8a7790",
"renesas,rcar-gen2-can";

2
arch/arm64/boot/dts/renesas/Makefile
View File

@ -76,9 +76,11 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb

5
arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi
View File

@ -5,6 +5,8 @@
* Copyright (C) 2021 Glider bv
*/
#include <dt-bindings/media/video-interfaces.h>
&csi40 {
status = "okay";
@ -105,6 +107,7 @@
port@4 {
reg = <4>;
max96712_out0: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
@ -125,6 +128,7 @@
port@4 {
reg = <4>;
max96712_out1: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
@ -146,6 +150,7 @@
port@4 {
reg = <4>;
max96712_out2: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;

22
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@ -2098,7 +2098,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee480000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -2107,7 +2107,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee4c0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 19>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -2116,7 +2116,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -2125,7 +2125,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed40000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -2134,7 +2134,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed80000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_A3IR>;
#iommu-cells = <1>;
};
@ -2143,7 +2143,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeedc0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -2152,7 +2152,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee80000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -2161,7 +2161,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeeec0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 15>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -2170,7 +2170,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -2179,7 +2179,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -2188,7 +2188,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef40000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 11>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};

8
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View File

@ -1059,7 +1059,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee480000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -1068,7 +1068,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee4c0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 19>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -1077,7 +1077,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -1086,7 +1086,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed40000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};

126
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@ -1655,6 +1655,14 @@
resets = <&cpg 709>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac1: dma-controller@e7351000 {
@ -1690,6 +1698,14 @@
resets = <&cpg 710>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
<&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
<&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
<&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
<&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
<&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
<&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
<&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
};
rcar_sound: sound@ec5a0000 {
@ -1761,6 +1777,115 @@
};
};
ipmmu_rt0: iommu@ee480000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee480000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_rt1: iommu@ee4c0000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee4c0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds0: iommu@eed00000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_hc: iommu@eed40000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed40000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ir: iommu@eed80000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed80000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_A3IR>;
#iommu-cells = <1>;
};
ipmmu_vc: iommu@eedc0000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeedc0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_3dg: iommu@eee00000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vi0: iommu@eee80000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee80000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vi1: iommu@eeec0000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeeec0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vip0: iommu@eef00000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vip1: iommu@eef40000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef40000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_mm: iommu@eefc0000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeefc0000 0 0x20000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a779g0",
"renesas,rcar-gen4-sdhi";
@ -1772,6 +1897,7 @@
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 706>;
max-frequency = <200000000>;
iommus = <&ipmmu_ds0 32>;
status = "disabled";
};

45
arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the RZ/{G2UL, Five} SMARC EVK PMOD parts
*
* Copyright (C) 2023 Renesas Electronics Corp.
*
*
* [Connection]
*
* SMARC EVK
* +----------------------------+
* |CN7 (PMOD1 PIN HEADER) |
* | SCI0_TXD pin7 |
* | SCI0_RXD pin8 |
* | Gnd pin11 |
* | Vcc pin12 |
* +----------------------------+
*
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
&pinctrl {
can0-stb-hog {
status = "disabled";
};
can1-stb-hog {
status = "disabled";
};
sci0_pins: sci0-pins {
pinmux = <RZG2L_PORT_PINMUX(2, 2, 5)>, /* TxD */
<RZG2L_PORT_PINMUX(2, 3, 5)>; /* RxD */
};
};
&sci0 {
pinctrl-0 = <&sci0_pins>;
pinctrl-names = "default";
status = "okay";
};

2
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View File

@ -564,9 +564,11 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_DMAC_ARESETN>,
<&cpg R9A07G043_DMAC_RST_ASYNC>;
reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};

81
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -618,6 +618,85 @@
status = "disabled";
};
cru: video@10830000 {
compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
reg = <0 0x10830000 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
<&cpg CPG_MOD R9A07G044_CRU_PCLK>,
<&cpg CPG_MOD R9A07G044_CRU_ACLK>;
clock-names = "video", "apb", "axi";
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
resets = <&cpg R9A07G044_CRU_PRESETN>,
<&cpg R9A07G044_CRU_ARESETN>;
reset-names = "presetn", "aresetn";
power-domains = <&cpg>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
cruparallel: endpoint@0 {
reg = <0>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
crucsi2: endpoint@0 {
reg = <0>;
remote-endpoint = <&csi2cru>;
};
};
};
};
csi2: csi2@10830400 {
compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
reg = <0 0x10830400 0 0xfc00>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
<&cpg CPG_MOD R9A07G044_CRU_VCLK>,
<&cpg CPG_MOD R9A07G044_CRU_PCLK>;
clock-names = "system", "video", "apb";
resets = <&cpg R9A07G044_CRU_PRESETN>,
<&cpg R9A07G044_CRU_CMN_RSTB>;
reset-names = "presetn", "cmn-rstb";
power-domains = <&cpg>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi2cru: endpoint@0 {
reg = <0>;
remote-endpoint = <&crucsi2>;
};
};
};
};
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0 0x11010000 0 0x10000>;
@ -740,9 +819,11 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_DMAC_ARESETN>,
<&cpg R9A07G044_DMAC_RST_ASYNC>;
reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};

21
arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree overlay for the RZ/G2L SMARC EVK with OV5645 camera
* connected to CSI and CRU enabled.
*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
#define OV5645_PARENT_I2C i2c0
#include "rz-smarc-cru-csi-ov5645.dtsi"
&ov5645 {
enable-gpios = <&pinctrl RZG2L_GPIO(2, 0) GPIO_ACTIVE_HIGH>;
reset-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>;
};

2
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@ -746,9 +746,11 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_DMAC_ARESETN>,
<&cpg R9A07G054_DMAC_RST_ASYNC>;
reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};

80
arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi Normal file
View File

@ -0,0 +1,80 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Common Device Tree for the RZ/G2L SMARC EVK (and alike EVKs) with
* OV5645 camera connected to CSI and CRU enabled.
*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
&{/} {
ov5645_vdddo_1v8: 1p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vdddo";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ov5645_vdda_2v8: 2p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vdda";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ov5645_vddd_1v5: 1p5v {
compatible = "regulator-fixed";
regulator-name = "camera_vddd";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
ov5645_fixed_clk: osc25250-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&cru {
status = "okay";
};
&csi2 {
status = "okay";
ports {
port@0 {
csi2_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&ov5645_ep>;
};
};
};
};
&OV5645_PARENT_I2C {
#address-cells = <1>;
#size-cells = <0>;
ov5645: camera@3c {
compatible = "ovti,ov5645";
reg = <0x3c>;
clocks = <&ov5645_fixed_clk>;
clock-frequency = <24000000>;
vdddo-supply = <&ov5645_vdddo_1v8>;
vdda-supply = <&ov5645_vdda_2v8>;
vddd-supply = <&ov5645_vddd_1v5>;
port {
ov5645_ep: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi2_in>;
};
};
};
};

1
include/dt-bindings/clock/r8a7779-clock.h
View File

@ -19,6 +19,7 @@
#define R8A7779_CLK_OUT 7
/* MSTP 0 */
#define R8A7779_CLK_PWM 5
#define R8A7779_CLK_HSPI 7
#define R8A7779_CLK_TMU2 14
#define R8A7779_CLK_TMU1 15