clk: exynos5250: register display block gate clocks to common clock framework
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi. Register it to common clock framework. Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -149,6 +149,12 @@ clock which they consume.
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wdt 336
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rtc 337
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tmu 338
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fimd1 339
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mie1 340
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dsim0 341
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dp 342
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mixer 343
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hdmi 345
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Example 1: An example of a clock controller node is listed below.
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@ -62,6 +62,7 @@
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#define GATE_IP_PERIS 0x10960
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#define SRC_CDREX 0x20200
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#define PLL_DIV2_SEL 0x20a24
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#define GATE_IP_DISP1 0x10928
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/*
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* Let each supported clock get a unique id. This id is used to lookup the clock
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@ -98,7 +99,7 @@ enum exynos5250_clks {
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spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
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hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
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tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
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wdt, rtc, tmu,
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wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
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nr_clks,
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};
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@ -150,6 +151,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
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GATE_IP_PERIS,
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SRC_CDREX,
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PLL_DIV2_SEL,
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GATE_IP_DISP1,
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};
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/* list of all parent clock list */
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@ -455,6 +457,12 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
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SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
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GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
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SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
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GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
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GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
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GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
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GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
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GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
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GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
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};
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static __initdata struct of_device_id ext_clk_match[] = {
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