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STi DT updates for v3.19, round 1. 

Highlights:
 -----------
  - Add SDHCI support for STiH41x B2020 boards
  - Add reset controllers to STiH407 SoC
  - Add MiPHY & SATA support to STiH416
  - Add Thermal supportto STiH416
  - Add Clock support to STiH407 SoC
 
 This tag also includes STiH407 bindings definitions for reset controller.
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Merge tag 'sti-dt-for-v3.19-1' of git://git.stlinux.com/devel/kernel/linux-sti into next/dt

Merge "STi DT updates for v3.19, round 1" from Maxime Coquelin:

Highlights:
-----------
 - Add SDHCI support for STiH41x B2020 boards
 - Add reset controllers to STiH407 SoC
 - Add MiPHY & SATA support to STiH416
 - Add Thermal supportto STiH416
 - Add Clock support to STiH407 SoC

This tag also includes STiH407 bindings definitions for reset controller.

* tag 'sti-dt-for-v3.19-1' of git://git.stlinux.com/devel/kernel/linux-sti:
  ARM: STi: DT: STiH407: Fix: clk-tmds-hdmi clock is missing
  ARM: STi: DT: STiH407: Add all defines for STiH407 DT clocks
  ARM: STi: DT: STiH407: 407 DT Entry for clockgenA9
  ARM: STi: DT: STiH407: 407 DT Entry for clockgen D0/D2/D3
  ARM: STi: DT: STiH407: 407 DT Entry for clockgen C0
  ARM: STi: DT: STiH407: 407 DT Entry for clockgen A0
  ARM: DT: STi: STiH416: Add DT node for ST's SATA device
  ARM: DT: STi: STiH416: Add DT node for MiPHY365x
  ARM: STi: DT: STiH416: Supply Thermal Controller Device Tree nodes
  ARM: STi: DT: Enable second sdhci controller for stih416 b2020 boards.
  ARM: STi: DT: Enable mmc0 for both stih415 and stih416 SoCs
  ARM: STi: DT: Add sdhci controller for stih415
  ARM: STi: DT: Add sdhci pin configuration for stih415
  ARM: STi: DT: Add sdhci controller for stih416
  ARM: STi: DT: Add sdhci pins for stih416
  ARM: sti: Add STiH407 reset controller support.
  ARM: sti: Add STiH407 Kconfig entry to select STIH407_RESET
  ARM: STi: DT: STiH41x: Convert all uppercase non-defines to lowercase
  reset: stih407: Add reset controllers DT bindings

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-11-08 16:39:12 -08:00
parent 1ba5568c01 43ca480c4e
commit 1749e1fc9e
14 changed files with 1003 additions and 341 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

293
arch/arm/boot/dts/stih407-clock.dtsi
View File

@ -5,8 +5,13 @@
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <dt-bindings/clock/stih407-clks.h>
/ { / {
clocks { clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* /*
* Fixed 30MHz oscillator inputs to SoC * Fixed 30MHz oscillator inputs to SoC
*/ */
@ -19,10 +24,59 @@
/* /*
* ARM Peripheral clock for timers * ARM Peripheral clock for timers
*/ */
arm_periph_clk: arm-periph-clk { arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-factor-clock";
clock-frequency = <600000000>;
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
/*
* A9 PLL.
*/
clockgen-a9@92b0000 {
compatible = "st,clkgen-c32";
reg = <0x92b0000 0xffff>;
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clockgen-a9-pll-odf";
};
};
/*
* ARM CPU related clocks.
*/
clk_m_a9: clk-m-a9@92b0000 {
#clock-cells = <0>;
compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
reg = <0x92b0000 0x10000>;
clocks = <&clockgen_a9_pll 0>,
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
};
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clock-div = <2>;
clock-mult = <1>;
}; };
/* /*
@ -35,5 +89,238 @@
clock-frequency = <200000000>; clock-frequency = <200000000>;
clock-output-names = "clk-s-icn-reg-0"; clock-output-names = "clk-s-icn-reg-0";
}; };
clockgen-a@090ff000 {
compatible = "st,clkgen-c32";
reg = <0x90ff000 0x1000>;
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll-ofd-0";
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
compatible = "st,flexgen";
#clock-cells = <1>;
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;
clock-output-names = "clk-ic-lmi0";
};
};
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs";
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-fs0-ch0",
"clk-s-c0-fs0-ch1",
"clk-s-c0-fs0-ch2",
"clk-s-c0-fs0-ch3";
};
clk_s_c0: clockgen-c@09103000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-pll0-odf-0";
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen";
clocks = <&clk_s_c0_pll0 0>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_quadfs 0>,
<&clk_s_c0_quadfs 1>,
<&clk_s_c0_quadfs 2>,
<&clk_s_c0_quadfs 3>,
<&clk_sysin>;
clock-output-names = "clk-icn-gpu",
"clk-fdma",
"clk-nand",
"clk-hva",
"clk-proc-stfe",
"clk-proc-tp",
"clk-rx-icn-dmu",
"clk-rx-icn-hva",
"clk-icn-cpu",
"clk-tx-icn-dmu",
"clk-mmc-0",
"clk-mmc-1",
"clk-jpegdec",
"clk-ext2fa9",
"clk-ic-bdisp-0",
"clk-ic-bdisp-1",
"clk-pp-dmu",
"clk-vid-dmu",
"clk-dss-lpc",
"clk-st231-aud-0",
"clk-st231-gp-1",
"clk-st231-dmu",
"clk-icn-lmi",
"clk-tx-icn-disp-1",
"clk-icn-sbc",
"clk-stfe-frc2",
"clk-eth-phy",
"clk-eth-ref-phyclk",
"clk-flash-promip",
"clk-main-disp",
"clk-aux-disp",
"clk-compo-dvp";
};
};
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-d0-fs0-ch0",
"clk-s-d0-fs0-ch1",
"clk-s-d0-fs0-ch2",
"clk-s-d0-fs0-ch3";
};
clockgen-d0@09104000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen";
clocks = <&clk_s_d0_quadfs 0>,
<&clk_s_d0_quadfs 1>,
<&clk_s_d0_quadfs 2>,
<&clk_s_d0_quadfs 3>,
<&clk_sysin>;
clock-output-names = "clk-pcm-0",
"clk-pcm-1",
"clk-pcm-2",
"clk-spdiff";
};
};
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-d2-fs0-ch0",
"clk-s-d2-fs0-ch1",
"clk-s-d2-fs0-ch2",
"clk-s-d2-fs0-ch3";
};
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clockgen-d2@x9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen";
clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_d2_quadfs 2>,
<&clk_s_d2_quadfs 3>,
<&clk_sysin>,
<&clk_sysin>,
<&clk_tmdsout_hdmi>;
clock-output-names = "clk-pix-main-disp",
"clk-pix-pip",
"clk-pix-gdp1",
"clk-pix-gdp2",
"clk-pix-gdp3",
"clk-pix-gdp4",
"clk-pix-aux-disp",
"clk-denc",
"clk-pix-hddac",
"clk-hddac",
"clk-sddac",
"clk-pix-dvo",
"clk-dvo",
"clk-pix-hdmi",
"clk-tmds-hdmi",
"clk-ref-hdmiphy";
};
};
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-d3-fs0-ch0",
"clk-s-d3-fs0-ch1",
"clk-s-d3-fs0-ch2",
"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
compatible = "st,clkgen-c32";
reg = <0x9107000 0x1000>;
clk_s_d3_flexgen: clk-s-d3-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen";
clocks = <&clk_s_d3_quadfs 0>,
<&clk_s_d3_quadfs 1>,
<&clk_s_d3_quadfs 2>,
<&clk_s_d3_quadfs 3>,
<&clk_sysin>;
clock-output-names = "clk-stfe-frc1",
"clk-tsout-0",
"clk-tsout-1",
"clk-mchi",
"clk-vsens-compo",
"clk-frc1-remote",
"clk-lpc-0",
"clk-lpc-1";
};
};
}; };
}; };

34
arch/arm/boot/dts/stih407.dtsi
View File

@ -8,6 +8,7 @@
*/ */
#include "stih407-clock.dtsi" #include "stih407-clock.dtsi"
#include "stih407-pinctrl.dtsi" #include "stih407-pinctrl.dtsi"
#include <dt-bindings/reset-controller/stih407-resets.h>
/ { / {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
@ -63,6 +64,21 @@
ranges; ranges;
compatible = "simple-bus"; compatible = "simple-bus";
powerdown: powerdown-controller {
compatible = "st,stih407-powerdown";
#reset-cells = <1>;
};
softreset: softreset-controller {
compatible = "st,stih407-softreset";
#reset-cells = <1>;
};
picophyreset: picophyreset-controller {
compatible = "st,stih407-picophyreset";
#reset-cells = <1>;
};
syscfg_sbc: sbc-syscfg@9620000 { syscfg_sbc: sbc-syscfg@9620000 {
compatible = "st,stih407-sbc-syscfg", "syscon"; compatible = "st,stih407-sbc-syscfg", "syscon";
reg = <0x9620000 0x1000>; reg = <0x9620000 0x1000>;
@ -104,7 +120,7 @@
interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial0>; pinctrl-0 = <&pinctrl_serial0>;
clocks = <&clk_ext2f_a9>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
status = "disabled"; status = "disabled";
}; };
@ -115,7 +131,7 @@
interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial1>; pinctrl-0 = <&pinctrl_serial1>;
clocks = <&clk_ext2f_a9>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
status = "disabled"; status = "disabled";
}; };
@ -126,7 +142,7 @@
interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2>; pinctrl-0 = <&pinctrl_serial2>;
clocks = <&clk_ext2f_a9>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
status = "disabled"; status = "disabled";
}; };
@ -158,7 +174,7 @@
compatible = "st,comms-ssc4-i2c"; compatible = "st,comms-ssc4-i2c";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x9840000 0x110>; reg = <0x9840000 0x110>;
clocks = <&clk_ext2f_a9>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
clock-names = "ssc"; clock-names = "ssc";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -171,7 +187,7 @@
compatible = "st,comms-ssc4-i2c"; compatible = "st,comms-ssc4-i2c";
reg = <0x9841000 0x110>; reg = <0x9841000 0x110>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_ext2f_a9>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
clock-names = "ssc"; clock-names = "ssc";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -184,7 +200,7 @@
compatible = "st,comms-ssc4-i2c"; compatible = "st,comms-ssc4-i2c";
reg = <0x9842000 0x110>; reg = <0x9842000 0x110>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_ext2f_a9>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
clock-names = "ssc"; clock-names = "ssc";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -197,7 +213,7 @@
compatible = "st,comms-ssc4-i2c"; compatible = "st,comms-ssc4-i2c";
reg = <0x9843000 0x110>; reg = <0x9843000 0x110>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_ext2f_a9>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
clock-names = "ssc"; clock-names = "ssc";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -210,7 +226,7 @@
compatible = "st,comms-ssc4-i2c"; compatible = "st,comms-ssc4-i2c";
reg = <0x9844000 0x110>; reg = <0x9844000 0x110>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_ext2f_a9>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
clock-names = "ssc"; clock-names = "ssc";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -223,7 +239,7 @@
compatible = "st,comms-ssc4-i2c"; compatible = "st,comms-ssc4-i2c";
reg = <0x9845000 0x110>; reg = <0x9845000 0x110>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_ext2f_a9>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
clock-names = "ssc"; clock-names = "ssc";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";

341
arch/arm/boot/dts/stih415-pinctrl.dtsi
View File

@ -11,33 +11,33 @@
/ { / {
aliases { aliases {
gpio0 = &PIO0; gpio0 = &pio0;
gpio1 = &PIO1; gpio1 = &pio1;
gpio2 = &PIO2; gpio2 = &pio2;
gpio3 = &PIO3; gpio3 = &pio3;
gpio4 = &PIO4; gpio4 = &pio4;
gpio5 = &PIO5; gpio5 = &pio5;
gpio6 = &PIO6; gpio6 = &pio6;
gpio7 = &PIO7; gpio7 = &pio7;
gpio8 = &PIO8; gpio8 = &pio8;
gpio9 = &PIO9; gpio9 = &pio9;
gpio10 = &PIO10; gpio10 = &pio10;
gpio11 = &PIO11; gpio11 = &pio11;
gpio12 = &PIO12; gpio12 = &pio12;
gpio13 = &PIO13; gpio13 = &pio13;
gpio14 = &PIO14; gpio14 = &pio14;
gpio15 = &PIO15; gpio15 = &pio15;
gpio16 = &PIO16; gpio16 = &pio16;
gpio17 = &PIO17; gpio17 = &pio17;
gpio18 = &PIO18; gpio18 = &pio18;
gpio19 = &PIO100; gpio19 = &pio100;
gpio20 = &PIO101; gpio20 = &pio101;
gpio21 = &PIO102; gpio21 = &pio102;
gpio22 = &PIO103; gpio22 = &pio103;
gpio23 = &PIO104; gpio23 = &pio104;
gpio24 = &PIO105; gpio24 = &pio105;
gpio25 = &PIO106; gpio25 = &pio106;
gpio26 = &PIO107; gpio26 = &pio107;
}; };
soc { soc {
@ -52,7 +52,7 @@
interrupt-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfe610000 0x5000>; ranges = <0 0xfe610000 0x5000>;
PIO0: gpio@fe610000 { pio0: gpio@fe610000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -60,7 +60,7 @@
reg = <0 0x100>; reg = <0 0x100>;
st,bank-name = "PIO0"; st,bank-name = "PIO0";
}; };
PIO1: gpio@fe611000 { pio1: gpio@fe611000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -68,7 +68,7 @@
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
st,bank-name = "PIO1"; st,bank-name = "PIO1";
}; };
PIO2: gpio@fe612000 { pio2: gpio@fe612000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -76,7 +76,7 @@
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
st,bank-name = "PIO2"; st,bank-name = "PIO2";
}; };
PIO3: gpio@fe613000 { pio3: gpio@fe613000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -84,7 +84,7 @@
reg = <0x3000 0x100>; reg = <0x3000 0x100>;
st,bank-name = "PIO3"; st,bank-name = "PIO3";
}; };
PIO4: gpio@fe614000 { pio4: gpio@fe614000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -96,8 +96,8 @@
sbc_serial1 { sbc_serial1 {
pinctrl_sbc_serial1:sbc_serial1 { pinctrl_sbc_serial1:sbc_serial1 {
st,pins { st,pins {
tx = <&PIO2 6 ALT3 OUT>; tx = <&pio2 6 ALT3 OUT>;
rx = <&PIO2 7 ALT3 IN>; rx = <&pio2 7 ALT3 IN>;
}; };
}; };
}; };
@ -105,15 +105,15 @@
keyscan { keyscan {
pinctrl_keyscan: keyscan { pinctrl_keyscan: keyscan {
st,pins { st,pins {
keyin0 = <&PIO0 2 ALT2 IN>; keyin0 = <&pio0 2 ALT2 IN>;
keyin1 = <&PIO0 3 ALT2 IN>; keyin1 = <&pio0 3 ALT2 IN>;
keyin2 = <&PIO0 4 ALT2 IN>; keyin2 = <&pio0 4 ALT2 IN>;
keyin3 = <&PIO2 6 ALT2 IN>; keyin3 = <&pio2 6 ALT2 IN>;
keyout0 = <&PIO1 6 ALT2 OUT>; keyout0 = <&pio1 6 ALT2 OUT>;
keyout1 = <&PIO1 7 ALT2 OUT>; keyout1 = <&pio1 7 ALT2 OUT>;
keyout2 = <&PIO0 6 ALT2 OUT>; keyout2 = <&pio0 6 ALT2 OUT>;
keyout3 = <&PIO2 7 ALT2 OUT>; keyout3 = <&pio2 7 ALT2 OUT>;
}; };
}; };
}; };
@ -121,8 +121,8 @@
sbc_i2c0 { sbc_i2c0 {
pinctrl_sbc_i2c0_default: sbc_i2c0-default { pinctrl_sbc_i2c0_default: sbc_i2c0-default {
st,pins { st,pins {
sda = <&PIO4 6 ALT1 BIDIR>; sda = <&pio4 6 ALT1 BIDIR>;
scl = <&PIO4 5 ALT1 BIDIR>; scl = <&pio4 5 ALT1 BIDIR>;
}; };
}; };
}; };
@ -130,8 +130,8 @@
sbc_i2c1 { sbc_i2c1 {
pinctrl_sbc_i2c1_default: sbc_i2c1-default { pinctrl_sbc_i2c1_default: sbc_i2c1-default {
st,pins { st,pins {
sda = <&PIO3 2 ALT2 BIDIR>; sda = <&pio3 2 ALT2 BIDIR>;
scl = <&PIO3 1 ALT2 BIDIR>; scl = <&pio3 1 ALT2 BIDIR>;
}; };
}; };
}; };
@ -139,7 +139,7 @@
rc{ rc{
pinctrl_ir: ir0 { pinctrl_ir: ir0 {
st,pins { st,pins {
ir = <&PIO4 0 ALT2 IN>; ir = <&pio4 0 ALT2 IN>;
}; };
}; };
}; };
@ -147,49 +147,49 @@
gmac1 { gmac1 {
pinctrl_mii1: mii1 { pinctrl_mii1: mii1 {
st,pins { st,pins {
txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
col = <&PIO0 7 ALT1 IN BYPASS 1000>; col = <&pio0 7 ALT1 IN BYPASS 1000>;
mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
crs = <&PIO1 2 ALT1 IN BYPASS 1000>; crs = <&pio1 2 ALT1 IN BYPASS 1000>;
mdint = <&PIO1 3 ALT1 IN BYPASS 0>; mdint = <&pio1 3 ALT1 IN BYPASS 0>;
rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>; phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>;
}; };
}; };
pinctrl_rgmii1: rgmii1-0 { pinctrl_rgmii1: rgmii1-0 {
st,pins { st,pins {
txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>; txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>;
txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>; txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>;
txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>; txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>;
txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>; txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>;
txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>; rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>; rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>; rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>; rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
}; };
}; };
}; };
@ -206,7 +206,7 @@
interrupt-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfee00000 0x8000>; ranges = <0 0xfee00000 0x8000>;
PIO5: gpio@fee00000 { pio5: gpio@fee00000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -214,7 +214,7 @@
reg = <0 0x100>; reg = <0 0x100>;
st,bank-name = "PIO5"; st,bank-name = "PIO5";
}; };
PIO6: gpio@fee01000 { pio6: gpio@fee01000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -222,7 +222,7 @@
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
st,bank-name = "PIO6"; st,bank-name = "PIO6";
}; };
PIO7: gpio@fee02000 { pio7: gpio@fee02000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -230,7 +230,7 @@
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
st,bank-name = "PIO7"; st,bank-name = "PIO7";
}; };
PIO8: gpio@fee03000 { pio8: gpio@fee03000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -238,7 +238,7 @@
reg = <0x3000 0x100>; reg = <0x3000 0x100>;
st,bank-name = "PIO8"; st,bank-name = "PIO8";
}; };
PIO9: gpio@fee04000 { pio9: gpio@fee04000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -246,7 +246,7 @@
reg = <0x4000 0x100>; reg = <0x4000 0x100>;
st,bank-name = "PIO9"; st,bank-name = "PIO9";
}; };
PIO10: gpio@fee05000 { pio10: gpio@fee05000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -254,7 +254,7 @@
reg = <0x5000 0x100>; reg = <0x5000 0x100>;
st,bank-name = "PIO10"; st,bank-name = "PIO10";
}; };
PIO11: gpio@fee06000 { pio11: gpio@fee06000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -262,7 +262,7 @@
reg = <0x6000 0x100>; reg = <0x6000 0x100>;
st,bank-name = "PIO11"; st,bank-name = "PIO11";
}; };
PIO12: gpio@fee07000 { pio12: gpio@fee07000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -274,8 +274,8 @@
i2c0 { i2c0 {
pinctrl_i2c0_default: i2c0-default { pinctrl_i2c0_default: i2c0-default {
st,pins { st,pins {
sda = <&PIO9 3 ALT1 BIDIR>; sda = <&pio9 3 ALT1 BIDIR>;
scl = <&PIO9 2 ALT1 BIDIR>; scl = <&pio9 2 ALT1 BIDIR>;
}; };
}; };
}; };
@ -283,8 +283,8 @@
i2c1 { i2c1 {
pinctrl_i2c1_default: i2c1-default { pinctrl_i2c1_default: i2c1-default {
st,pins { st,pins {
sda = <&PIO12 1 ALT1 BIDIR>; sda = <&pio12 1 ALT1 BIDIR>;
scl = <&PIO12 0 ALT1 BIDIR>; scl = <&pio12 0 ALT1 BIDIR>;
}; };
}; };
}; };
@ -301,7 +301,7 @@
interrupt-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfe820000 0x8000>; ranges = <0 0xfe820000 0x8000>;
PIO13: gpio@fe820000 { pio13: gpio@fe820000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -309,7 +309,7 @@
reg = <0 0x100>; reg = <0 0x100>;
st,bank-name = "PIO13"; st,bank-name = "PIO13";
}; };
PIO14: gpio@fe821000 { pio14: gpio@fe821000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -317,7 +317,7 @@
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
st,bank-name = "PIO14"; st,bank-name = "PIO14";
}; };
PIO15: gpio@fe822000 { pio15: gpio@fe822000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -325,7 +325,7 @@
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
st,bank-name = "PIO15"; st,bank-name = "PIO15";
}; };
PIO16: gpio@fe823000 { pio16: gpio@fe823000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -333,7 +333,7 @@
reg = <0x3000 0x100>; reg = <0x3000 0x100>;
st,bank-name = "PIO16"; st,bank-name = "PIO16";
}; };
PIO17: gpio@fe824000 { pio17: gpio@fe824000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -341,7 +341,7 @@
reg = <0x4000 0x100>; reg = <0x4000 0x100>;
st,bank-name = "PIO17"; st,bank-name = "PIO17";
}; };
PIO18: gpio@fe825000 { pio18: gpio@fe825000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -353,8 +353,8 @@
serial2 { serial2 {
pinctrl_serial2: serial2-0 { pinctrl_serial2: serial2-0 {
st,pins { st,pins {
tx = <&PIO17 4 ALT2 OUT>; tx = <&pio17 4 ALT2 OUT>;
rx = <&PIO17 5 ALT2 IN>; rx = <&pio17 5 ALT2 IN>;
}; };
}; };
}; };
@ -362,73 +362,94 @@
gmac0{ gmac0{
pinctrl_mii0: mii0 { pinctrl_mii0: mii0 {
st,pins { st,pins {
mdint = <&PIO13 6 ALT2 IN BYPASS 0>; mdint = <&pio13 6 ALT2 IN BYPASS 0>;
txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
crs = <&PIO15 2 ALT2 IN BYPASS 1000>; crs = <&pio15 2 ALT2 IN BYPASS 1000>;
col = <&PIO15 3 ALT2 IN BYPASS 1000>; col = <&pio15 3 ALT2 IN BYPASS 1000>;
mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>; phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>;
}; };
}; };
pinctrl_gmii0: gmii0 { pinctrl_gmii0: gmii0 {
st,pins { st,pins {
mdint = <&PIO13 6 ALT2 IN BYPASS 0>; mdint = <&pio13 6 ALT2 IN BYPASS 0>;
mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
crs = <&PIO15 2 ALT2 IN BYPASS 1000>; crs = <&pio15 2 ALT2 IN BYPASS 1000>;
col = <&PIO15 3 ALT2 IN BYPASS 1000>; col = <&pio15 3 ALT2 IN BYPASS 1000>;
rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>; clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>;
phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
}; };
}; };
}; };
mmc0 {
pinctrl_mmc0: mmc0 {
st,pins {
mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
wp = <&pio15 3 ALT4 IN>;
data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
pwr = <&pio17 1 ALT4 OUT>;
cd = <&pio17 2 ALT4 IN>;
led = <&pio17 3 ALT4 OUT>;
};
};
};
}; };
pin-controller-left { pin-controller-left {
@ -442,7 +463,7 @@
interrupt-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfd6b0000 0x3000>; ranges = <0 0xfd6b0000 0x3000>;
PIO100: gpio@fd6b0000 { pio100: gpio@fd6b0000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -450,7 +471,7 @@
reg = <0 0x100>; reg = <0 0x100>;
st,bank-name = "PIO100"; st,bank-name = "PIO100";
}; };
PIO101: gpio@fd6b1000 { pio101: gpio@fd6b1000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -458,7 +479,7 @@
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
st,bank-name = "PIO101"; st,bank-name = "PIO101";
}; };
PIO102: gpio@fd6b2000 { pio102: gpio@fd6b2000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -479,7 +500,7 @@
interrupt-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfd330000 0x5000>; ranges = <0 0xfd330000 0x5000>;
PIO103: gpio@fd330000 { pio103: gpio@fd330000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -487,7 +508,7 @@
reg = <0 0x100>; reg = <0 0x100>;
st,bank-name = "PIO103"; st,bank-name = "PIO103";
}; };
PIO104: gpio@fd331000 { pio104: gpio@fd331000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -495,7 +516,7 @@
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
st,bank-name = "PIO104"; st,bank-name = "PIO104";
}; };
PIO105: gpio@fd332000 { pio105: gpio@fd332000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -503,7 +524,7 @@
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
st,bank-name = "PIO105"; st,bank-name = "PIO105";
}; };
PIO106: gpio@fd333000 { pio106: gpio@fd333000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -511,7 +532,7 @@
reg = <0x3000 0x100>; reg = <0x3000 0x100>;
st,bank-name = "PIO106"; st,bank-name = "PIO106";
}; };
PIO107: gpio@fd334000 { pio107: gpio@fd334000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;

12
arch/arm/boot/dts/stih415.dtsi
View File

@ -218,5 +218,17 @@
resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>,
<&softreset STIH415_KEYSCAN_SOFTRESET>; <&softreset STIH415_KEYSCAN_SOFTRESET>;
}; };
mmc0: sdhci@fe81e000 {
compatible = "st,sdhci";
status = "disabled";
reg = <0xfe81e000 0x1000>;
interrupts = <GIC_SPI 145 IRQ_TYPE_NONE>;
interrupt-names = "mmcirq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0>;
clock-names = "mmc";
clocks = <&clk_s_a1_ls 1>;
};
}; };
}; };

22
arch/arm/boot/dts/stih416-b2020.dts
View File

@ -12,4 +12,26 @@
/ { / {
model = "STiH416 B2020"; model = "STiH416 B2020";
compatible = "st,stih416-b2020", "st,stih416"; compatible = "st,stih416-b2020", "st,stih416";
soc {
mmc1: sdhci@fe81f000 {
status = "okay";
bus-width = <8>;
non-removable;
};
miphy365x_phy: miphy365x@fe382000 {
phy_port0: port@fe382000 {
st,sata-gen = <3>;
};
phy_port1: port@fe38a000 {
st,pcie-tx-pol-inv;
};
};
sata0: sata@fe380000{
status = "okay";
};
};
}; };

26
arch/arm/boot/dts/stih416-b2020e.dts
View File

@ -19,17 +19,37 @@
red { red {
#gpio-cells = <1>; #gpio-cells = <1>;
label = "Front Panel LED"; label = "Front Panel LED";
gpios = <&PIO4 1>; gpios = <&pio4 1>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
green { green {
gpios = <&PIO1 3>; gpios = <&pio1 3>;
default-state = "off"; default-state = "off";
}; };
}; };
ethernet1: dwmac@fef08000 { ethernet1: dwmac@fef08000 {
snps,reset-gpio = <&PIO0 7>; snps,reset-gpio = <&pio0 7>;
};
mmc1: sdhci@fe81f000 {
status = "okay";
bus-width = <8>;
non-removable;
};
miphy365x_phy: miphy365x@fe382000 {
phy_port0: port@fe382000 {
st,sata-gen = <3>;
};
phy_port1: port@fe38a000 {
st,pcie-tx-pol-inv;
};
};
sata0: sata@fe380000{
status = "okay";
}; };
}; };
}; };

359
arch/arm/boot/dts/stih416-pinctrl.dtsi
View File

@ -12,36 +12,36 @@
/ { / {
aliases { aliases {
gpio0 = &PIO0; gpio0 = &pio0;
gpio1 = &PIO1; gpio1 = &pio1;
gpio2 = &PIO2; gpio2 = &pio2;
gpio3 = &PIO3; gpio3 = &pio3;
gpio4 = &PIO4; gpio4 = &pio4;
gpio5 = &PIO40; gpio5 = &pio40;
gpio6 = &PIO5; gpio6 = &pio5;
gpio7 = &PIO6; gpio7 = &pio6;
gpio8 = &PIO7; gpio8 = &pio7;
gpio9 = &PIO8; gpio9 = &pio8;
gpio10 = &PIO9; gpio10 = &pio9;
gpio11 = &PIO10; gpio11 = &pio10;
gpio12 = &PIO11; gpio12 = &pio11;
gpio13 = &PIO12; gpio13 = &pio12;
gpio14 = &PIO30; gpio14 = &pio30;
gpio15 = &PIO31; gpio15 = &pio31;
gpio16 = &PIO13; gpio16 = &pio13;
gpio17 = &PIO14; gpio17 = &pio14;
gpio18 = &PIO15; gpio18 = &pio15;
gpio19 = &PIO16; gpio19 = &pio16;
gpio20 = &PIO17; gpio20 = &pio17;
gpio21 = &PIO18; gpio21 = &pio18;
gpio22 = &PIO100; gpio22 = &pio100;
gpio23 = &PIO101; gpio23 = &pio101;
gpio24 = &PIO102; gpio24 = &pio102;
gpio25 = &PIO103; gpio25 = &pio103;
gpio26 = &PIO104; gpio26 = &pio104;
gpio27 = &PIO105; gpio27 = &pio105;
gpio28 = &PIO106; gpio28 = &pio106;
gpio29 = &PIO107; gpio29 = &pio107;
}; };
soc { soc {
@ -56,7 +56,7 @@
interrupt-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfe610000 0x6000>; ranges = <0 0xfe610000 0x6000>;
PIO0: gpio@fe610000 { pio0: gpio@fe610000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -64,7 +64,7 @@
reg = <0 0x100>; reg = <0 0x100>;
st,bank-name = "PIO0"; st,bank-name = "PIO0";
}; };
PIO1: gpio@fe611000 { pio1: gpio@fe611000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -72,7 +72,7 @@
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
st,bank-name = "PIO1"; st,bank-name = "PIO1";
}; };
PIO2: gpio@fe612000 { pio2: gpio@fe612000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -80,7 +80,7 @@
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
st,bank-name = "PIO2"; st,bank-name = "PIO2";
}; };
PIO3: gpio@fe613000 { pio3: gpio@fe613000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -88,7 +88,7 @@
reg = <0x3000 0x100>; reg = <0x3000 0x100>;
st,bank-name = "PIO3"; st,bank-name = "PIO3";
}; };
PIO4: gpio@fe614000 { pio4: gpio@fe614000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -96,7 +96,7 @@
reg = <0x4000 0x100>; reg = <0x4000 0x100>;
st,bank-name = "PIO4"; st,bank-name = "PIO4";
}; };
PIO40: gpio@fe615000 { pio40: gpio@fe615000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -109,15 +109,15 @@
rc{ rc{
pinctrl_ir: ir0 { pinctrl_ir: ir0 {
st,pins { st,pins {
ir = <&PIO4 0 ALT2 IN>; ir = <&pio4 0 ALT2 IN>;
}; };
}; };
}; };
sbc_serial1 { sbc_serial1 {
pinctrl_sbc_serial1: sbc_serial1 { pinctrl_sbc_serial1: sbc_serial1 {
st,pins { st,pins {
tx = <&PIO2 6 ALT3 OUT>; tx = <&pio2 6 ALT3 OUT>;
rx = <&PIO2 7 ALT3 IN>; rx = <&pio2 7 ALT3 IN>;
}; };
}; };
}; };
@ -125,15 +125,15 @@
keyscan { keyscan {
pinctrl_keyscan: keyscan { pinctrl_keyscan: keyscan {
st,pins { st,pins {
keyin0 = <&PIO0 2 ALT2 IN>; keyin0 = <&pio0 2 ALT2 IN>;
keyin1 = <&PIO0 3 ALT2 IN>; keyin1 = <&pio0 3 ALT2 IN>;
keyin2 = <&PIO0 4 ALT2 IN>; keyin2 = <&pio0 4 ALT2 IN>;
keyin3 = <&PIO2 6 ALT2 IN>; keyin3 = <&pio2 6 ALT2 IN>;
keyout0 = <&PIO1 6 ALT2 OUT>; keyout0 = <&pio1 6 ALT2 OUT>;
keyout1 = <&PIO1 7 ALT2 OUT>; keyout1 = <&pio1 7 ALT2 OUT>;
keyout2 = <&PIO0 6 ALT2 OUT>; keyout2 = <&pio0 6 ALT2 OUT>;
keyout3 = <&PIO2 7 ALT2 OUT>; keyout3 = <&pio2 7 ALT2 OUT>;
}; };
}; };
}; };
@ -141,8 +141,8 @@
sbc_i2c0 { sbc_i2c0 {
pinctrl_sbc_i2c0_default: sbc_i2c0-default { pinctrl_sbc_i2c0_default: sbc_i2c0-default {
st,pins { st,pins {
sda = <&PIO4 6 ALT1 BIDIR>; sda = <&pio4 6 ALT1 BIDIR>;
scl = <&PIO4 5 ALT1 BIDIR>; scl = <&pio4 5 ALT1 BIDIR>;
}; };
}; };
}; };
@ -150,8 +150,8 @@
sbc_i2c1 { sbc_i2c1 {
pinctrl_sbc_i2c1_default: sbc_i2c1-default { pinctrl_sbc_i2c1_default: sbc_i2c1-default {
st,pins { st,pins {
sda = <&PIO3 2 ALT2 BIDIR>; sda = <&pio3 2 ALT2 BIDIR>;
scl = <&PIO3 1 ALT2 BIDIR>; scl = <&pio3 1 ALT2 BIDIR>;
}; };
}; };
}; };
@ -159,51 +159,51 @@
gmac1 { gmac1 {
pinctrl_mii1: mii1 { pinctrl_mii1: mii1 {
st,pins { st,pins {
txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
col = <&PIO0 7 ALT1 IN BYPASS 1000>; col = <&pio0 7 ALT1 IN BYPASS 1000>;
mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>; mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
crs = <&PIO1 2 ALT1 IN BYPASS 1000>; crs = <&pio1 2 ALT1 IN BYPASS 1000>;
mdint = <&PIO1 3 ALT1 IN BYPASS 0>; mdint = <&pio1 3 ALT1 IN BYPASS 0>;
rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>; phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
}; };
}; };
pinctrl_rgmii1: rgmii1-0 { pinctrl_rgmii1: rgmii1-0 {
st,pins { st,pins {
txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>; txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>; txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>; txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>; txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>; rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>; rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>; rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>; rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;
rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
}; };
}; };
}; };
@ -220,7 +220,7 @@
interrupt-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfee00000 0x10000>; ranges = <0 0xfee00000 0x10000>;
PIO5: gpio@fee00000 { pio5: gpio@fee00000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -228,7 +228,7 @@
reg = <0 0x100>; reg = <0 0x100>;
st,bank-name = "PIO5"; st,bank-name = "PIO5";
}; };
PIO6: gpio@fee01000 { pio6: gpio@fee01000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -236,7 +236,7 @@
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
st,bank-name = "PIO6"; st,bank-name = "PIO6";
}; };
PIO7: gpio@fee02000 { pio7: gpio@fee02000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -244,7 +244,7 @@
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
st,bank-name = "PIO7"; st,bank-name = "PIO7";
}; };
PIO8: gpio@fee03000 { pio8: gpio@fee03000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -252,7 +252,7 @@
reg = <0x3000 0x100>; reg = <0x3000 0x100>;
st,bank-name = "PIO8"; st,bank-name = "PIO8";
}; };
PIO9: gpio@fee04000 { pio9: gpio@fee04000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -260,7 +260,7 @@
reg = <0x4000 0x100>; reg = <0x4000 0x100>;
st,bank-name = "PIO9"; st,bank-name = "PIO9";
}; };
PIO10: gpio@fee05000 { pio10: gpio@fee05000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -268,7 +268,7 @@
reg = <0x5000 0x100>; reg = <0x5000 0x100>;
st,bank-name = "PIO10"; st,bank-name = "PIO10";
}; };
PIO11: gpio@fee06000 { pio11: gpio@fee06000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -276,7 +276,7 @@
reg = <0x6000 0x100>; reg = <0x6000 0x100>;
st,bank-name = "PIO11"; st,bank-name = "PIO11";
}; };
PIO12: gpio@fee07000 { pio12: gpio@fee07000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -284,7 +284,7 @@
reg = <0x7000 0x100>; reg = <0x7000 0x100>;
st,bank-name = "PIO12"; st,bank-name = "PIO12";
}; };
PIO30: gpio@fee08000 { pio30: gpio@fee08000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -292,7 +292,7 @@
reg = <0x8000 0x100>; reg = <0x8000 0x100>;
st,bank-name = "PIO30"; st,bank-name = "PIO30";
}; };
PIO31: gpio@fee09000 { pio31: gpio@fee09000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -304,7 +304,7 @@
serial2-oe { serial2-oe {
pinctrl_serial2_oe: serial2-1 { pinctrl_serial2_oe: serial2-1 {
st,pins { st,pins {
output-enable = <&PIO11 3 ALT2 OUT>; output-enable = <&pio11 3 ALT2 OUT>;
}; };
}; };
}; };
@ -312,8 +312,8 @@
i2c0 { i2c0 {
pinctrl_i2c0_default: i2c0-default { pinctrl_i2c0_default: i2c0-default {
st,pins { st,pins {
sda = <&PIO9 3 ALT1 BIDIR>; sda = <&pio9 3 ALT1 BIDIR>;
scl = <&PIO9 2 ALT1 BIDIR>; scl = <&pio9 2 ALT1 BIDIR>;
}; };
}; };
}; };
@ -321,8 +321,8 @@
i2c1 { i2c1 {
pinctrl_i2c1_default: i2c1-default { pinctrl_i2c1_default: i2c1-default {
st,pins { st,pins {
sda = <&PIO12 1 ALT1 BIDIR>; sda = <&pio12 1 ALT1 BIDIR>;
scl = <&PIO12 0 ALT1 BIDIR>; scl = <&pio12 0 ALT1 BIDIR>;
}; };
}; };
}; };
@ -330,12 +330,12 @@
fsm { fsm {
pinctrl_fsm: fsm { pinctrl_fsm: fsm {
st,pins { st,pins {
spi-fsm-clk = <&PIO12 2 ALT1 OUT>; spi-fsm-clk = <&pio12 2 ALT1 OUT>;
spi-fsm-cs = <&PIO12 3 ALT1 OUT>; spi-fsm-cs = <&pio12 3 ALT1 OUT>;
spi-fsm-mosi = <&PIO12 4 ALT1 OUT>; spi-fsm-mosi = <&pio12 4 ALT1 OUT>;
spi-fsm-miso = <&PIO12 5 ALT1 IN>; spi-fsm-miso = <&pio12 5 ALT1 IN>;
spi-fsm-hol = <&PIO12 6 ALT1 OUT>; spi-fsm-hol = <&pio12 6 ALT1 OUT>;
spi-fsm-wp = <&PIO12 7 ALT1 OUT>; spi-fsm-wp = <&pio12 7 ALT1 OUT>;
}; };
}; };
}; };
@ -352,7 +352,7 @@
interrupt-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfe820000 0x6000>; ranges = <0 0xfe820000 0x6000>;
PIO13: gpio@fe820000 { pio13: gpio@fe820000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -360,7 +360,7 @@
reg = <0 0x100>; reg = <0 0x100>;
st,bank-name = "PIO13"; st,bank-name = "PIO13";
}; };
PIO14: gpio@fe821000 { pio14: gpio@fe821000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -368,7 +368,7 @@
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
st,bank-name = "PIO14"; st,bank-name = "PIO14";
}; };
PIO15: gpio@fe822000 { pio15: gpio@fe822000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -376,7 +376,7 @@
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
st,bank-name = "PIO15"; st,bank-name = "PIO15";
}; };
PIO16: gpio@fe823000 { pio16: gpio@fe823000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -384,7 +384,7 @@
reg = <0x3000 0x100>; reg = <0x3000 0x100>;
st,bank-name = "PIO16"; st,bank-name = "PIO16";
}; };
PIO17: gpio@fe824000 { pio17: gpio@fe824000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -392,7 +392,7 @@
reg = <0x4000 0x100>; reg = <0x4000 0x100>;
st,bank-name = "PIO17"; st,bank-name = "PIO17";
}; };
PIO18: gpio@fe825000 { pio18: gpio@fe825000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -405,8 +405,8 @@
serial2 { serial2 {
pinctrl_serial2: serial2-0 { pinctrl_serial2: serial2-0 {
st,pins { st,pins {
tx = <&PIO17 4 ALT2 OUT>; tx = <&pio17 4 ALT2 OUT>;
rx = <&PIO17 5 ALT2 IN>; rx = <&pio17 5 ALT2 IN>;
}; };
}; };
}; };
@ -414,28 +414,28 @@
gmac0 { gmac0 {
pinctrl_mii0: mii0 { pinctrl_mii0: mii0 {
st,pins { st,pins {
mdint = <&PIO13 6 ALT2 IN BYPASS 0>; mdint = <&pio13 6 ALT2 IN BYPASS 0>;
txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
crs = <&PIO15 2 ALT2 IN BYPASS 1000>; crs = <&pio15 2 ALT2 IN BYPASS 1000>;
col = <&PIO15 3 ALT2 IN BYPASS 1000>; col = <&pio15 3 ALT2 IN BYPASS 1000>;
mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>; mdio= <&pio15 4 ALT2 OUT BYPASS 1500>;
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>; phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>;
}; };
}; };
@ -445,25 +445,64 @@
}; };
pinctrl_rgmii0: rgmii0 { pinctrl_rgmii0: rgmii0 {
st,pins { st,pins {
phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>; txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>; txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>; txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>; txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>;
txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>; txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>;
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
mdio = <&PIO15 4 ALT2 OUT BYPASS 0>; mdio = <&pio15 4 ALT2 OUT BYPASS 0>;
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>; rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>; rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>;
rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>; rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>;
rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>; rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>;
rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>; rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>; rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;
clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>; clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;
};
};
};
mmc0 {
pinctrl_mmc0: mmc0 {
st,pins {
mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
wp = <&pio15 3 ALT4 IN>;
data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
pwr = <&pio17 1 ALT4 OUT>;
cd = <&pio17 2 ALT4 IN>;
led = <&pio17 3 ALT4 OUT>;
};
};
};
mmc1 {
pinctrl_mmc1: mmc1 {
st,pins {
mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>;
data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>;
data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>;
data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>;
data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>;
cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>;
data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>;
data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>;
data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>;
data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>;
pwr = <&pio16 2 ALT3 OUT>;
nreset = <&pio13 6 ALT3 OUT>;
}; };
}; };
}; };
@ -480,7 +519,7 @@
interrupt-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfd6b0000 0x3000>; ranges = <0 0xfd6b0000 0x3000>;
PIO100: gpio@fd6b0000 { pio100: gpio@fd6b0000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -488,7 +527,7 @@
reg = <0 0x100>; reg = <0 0x100>;
st,bank-name = "PIO100"; st,bank-name = "PIO100";
}; };
PIO101: gpio@fd6b1000 { pio101: gpio@fd6b1000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -496,7 +535,7 @@
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
st,bank-name = "PIO101"; st,bank-name = "PIO101";
}; };
PIO102: gpio@fd6b2000 { pio102: gpio@fd6b2000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -517,7 +556,7 @@
interrupt-names = "irqmux"; interrupt-names = "irqmux";
ranges = <0 0xfd330000 0x5000>; ranges = <0 0xfd330000 0x5000>;
PIO103: gpio@fd330000 { pio103: gpio@fd330000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -525,7 +564,7 @@
reg = <0 0x100>; reg = <0 0x100>;
st,bank-name = "PIO103"; st,bank-name = "PIO103";
}; };
PIO104: gpio@fd331000 { pio104: gpio@fd331000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -533,7 +572,7 @@
reg = <0x1000 0x100>; reg = <0x1000 0x100>;
st,bank-name = "PIO104"; st,bank-name = "PIO104";
}; };
PIO105: gpio@fd332000 { pio105: gpio@fd332000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -541,7 +580,7 @@
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
st,bank-name = "PIO105"; st,bank-name = "PIO105";
}; };
PIO106: gpio@fd333000 { pio106: gpio@fd333000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;
@ -550,7 +589,7 @@
st,bank-name = "PIO106"; st,bank-name = "PIO106";
}; };
PIO107: gpio@fd334000 { pio107: gpio@fd334000 {
gpio-controller; gpio-controller;
#gpio-cells = <1>; #gpio-cells = <1>;
interrupt-controller; interrupt-controller;

80
arch/arm/boot/dts/stih416.dtsi
View File

@ -9,6 +9,8 @@
#include "stih41x.dtsi" #include "stih41x.dtsi"
#include "stih416-clock.dtsi" #include "stih416-clock.dtsi"
#include "stih416-pinctrl.dtsi" #include "stih416-pinctrl.dtsi"
#include <dt-bindings/phy/phy-miphy365x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset-controller/stih416-resets.h> #include <dt-bindings/reset-controller/stih416-resets.h>
/ { / {
@ -236,5 +238,83 @@
resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
<&softreset STIH416_KEYSCAN_SOFTRESET>; <&softreset STIH416_KEYSCAN_SOFTRESET>;
}; };
temp0 {
compatible = "st,stih416-sas-thermal";
clock-names = "thermal";
clocks = <&clockgen_c_vcc 14>;
status = "okay";
};
temp1@fdfe8000 {
compatible = "st,stih416-mpe-thermal";
reg = <0xfdfe8000 0x10>;
clocks = <&clockgen_e 3>;
clock-names = "thermal";
interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
status = "okay";
};
mmc0: sdhci@fe81e000 {
compatible = "st,sdhci";
status = "disabled";
reg = <0xfe81e000 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
interrupt-names = "mmcirq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0>;
clock-names = "mmc";
clocks = <&clk_s_a1_ls 1>;
};
mmc1: sdhci@fe81f000 {
compatible = "st,sdhci";
status = "disabled";
reg = <0xfe81f000 0x1000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
interrupt-names = "mmcirq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1>;
clock-names = "mmc";
clocks = <&clk_s_a1_ls 8>;
};
miphy365x_phy: miphy365x@fe382000 {
compatible = "st,miphy365x-phy";
st,syscfg = <&syscfg_rear>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
phy_port0: port@fe382000 {
#phy-cells = <1>;
reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
reg-names = "sata", "pcie", "syscfg";
};
phy_port1: port@fe38a000 {
#phy-cells = <1>;
reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
reg-names = "sata", "pcie", "syscfg";
};
};
sata0: sata@fe380000 {
compatible = "st,sti-ahci";
reg = <0xfe380000 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
interrupt-names = "hostc";
phys = <&phy_port0 MIPHY_TYPE_SATA>;
phy-names = "sata-phy";
resets = <&powerdown STIH416_SATA0_POWERDOWN>,
<&softreset STIH416_SATA0_SOFTRESET>;
reset-names = "pwr-dwn", "sw-rst";
clock-names = "ahci_clk";
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
status = "disabled";
};
}; };
}; };

6
arch/arm/boot/dts/stih41x-b2000.dtsi
View File

@ -35,7 +35,7 @@
fp_led { fp_led {
#gpio-cells = <1>; #gpio-cells = <1>;
label = "Front Panel LED"; label = "Front Panel LED";
gpios = <&PIO105 7>; gpios = <&pio105 7>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
}; };
@ -55,7 +55,7 @@
phy-mode = "mii"; phy-mode = "mii";
pinctrl-0 = <&pinctrl_mii0>; pinctrl-0 = <&pinctrl_mii0>;
snps,reset-gpio = <&PIO106 2>; snps,reset-gpio = <&pio106 2>;
snps,reset-active-low; snps,reset-active-low;
snps,reset-delays-us = <0 10000 10000>; snps,reset-delays-us = <0 10000 10000>;
}; };
@ -65,7 +65,7 @@
phy-mode = "mii"; phy-mode = "mii";
st,tx-retime-src = "txclk"; st,tx-retime-src = "txclk";
snps,reset-gpio = <&PIO4 7>; snps,reset-gpio = <&pio4 7>;
snps,reset-active-low; snps,reset-active-low;
snps,reset-delays-us = <0 10000 10000>; snps,reset-delays-us = <0 10000 10000>;
}; };

10
arch/arm/boot/dts/stih41x-b2020.dtsi
View File

@ -32,11 +32,11 @@
red { red {
#gpio-cells = <1>; #gpio-cells = <1>;
label = "Front Panel LED"; label = "Front Panel LED";
gpios = <&PIO4 1>; gpios = <&pio4 1>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
green { green {
gpios = <&PIO4 7>; gpios = <&pio4 7>;
default-state = "off"; default-state = "off";
}; };
}; };
@ -68,11 +68,15 @@
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
max-speed = <1000>; max-speed = <1000>;
st,tx-retime-src = "clk_125"; st,tx-retime-src = "clk_125";
snps,reset-gpio = <&PIO3 0>; snps,reset-gpio = <&pio3 0>;
snps,reset-active-low; snps,reset-active-low;
snps,reset-delays-us = <0 10000 10000>; snps,reset-delays-us = <0 10000 10000>;
pinctrl-0 = <&pinctrl_rgmii1>; pinctrl-0 = <&pinctrl_rgmii1>;
}; };
mmc0: sdhci@fe81e000 {
bus-width = <8>;
};
}; };
}; };

4
arch/arm/boot/dts/stih41x-b2020x.dtsi
View File

@ -8,6 +8,10 @@
*/ */
/ { / {
soc { soc {
mmc0: sdhci@fe81e000 {
status = "okay";
};
spifsm: spifsm@fe902000 { spifsm: spifsm@fe902000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;

10
arch/arm/mach-sti/Kconfig
View File

@ -42,4 +42,14 @@ config SOC_STIH416
and other digital audio/video applications using Flattened Device and other digital audio/video applications using Flattened Device
Trees. Trees.
config SOC_STIH407
bool "STiH407 STMicroelectronics Consumer Electronics family"
default y
select STIH407_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH407 parts, targetted at set-top-box
and other digital audio/video applications using Flattened Device
Trees.
endif endif

86
include/dt-bindings/clock/stih407-clks.h Normal file
View File

@ -0,0 +1,86 @@
/*
* This header provides constants clk index STMicroelectronics
* STiH407 SoC.
*/
#ifndef _DT_BINDINGS_CLK_STIH407
#define _DT_BINDINGS_CLK_STIH407
/* CLOCKGEN C0 */
#define CLK_ICN_GPU 0
#define CLK_FDMA 1
#define CLK_NAND 2
#define CLK_HVA 3
#define CLK_PROC_STFE 4
#define CLK_PROC_TP 5
#define CLK_RX_ICN_DMU 6
#define CLK_RX_ICN_DISP_0 6
#define CLK_RX_ICN_DISP_1 6
#define CLK_RX_ICN_HVA 7
#define CLK_RX_ICN_TS 7
#define CLK_ICN_CPU 8
#define CLK_TX_ICN_DMU 9
#define CLK_TX_ICN_HVA 9
#define CLK_TX_ICN_TS 9
#define CLK_ICN_COMPO 9
#define CLK_MMC_0 10
#define CLK_MMC_1 11
#define CLK_JPEGDEC 12
#define CLK_ICN_REG 13
#define CLK_TRACE_A9 13
#define CLK_PTI_STM 13
#define CLK_EXT2F_A9 13
#define CLK_IC_BDISP_0 14
#define CLK_IC_BDISP_1 15
#define CLK_PP_DMU 16
#define CLK_VID_DMU 17
#define CLK_DSS_LPC 18
#define CLK_ST231_AUD_0 19
#define CLK_ST231_GP_0 19
#define CLK_ST231_GP_1 20
#define CLK_ST231_DMU 21
#define CLK_ICN_LMI 22
#define CLK_TX_ICN_DISP_0 23
#define CLK_TX_ICN_DISP_1 23
#define CLK_ICN_SBC 24
#define CLK_STFE_FRC2 25
#define CLK_ETH_PHY 26
#define CLK_ETH_REF_PHYCLK 27
#define CLK_FLASH_PROMIP 28
#define CLK_MAIN_DISP 29
#define CLK_AUX_DISP 30
#define CLK_COMPO_DVP 31
/* CLOCKGEN D0 */
#define CLK_PCM_0 0
#define CLK_PCM_1 1
#define CLK_PCM_2 2
#define CLK_SPDIFF 3
/* CLOCKGEN D2 */
#define CLK_PIX_MAIN_DISP 0
#define CLK_PIX_PIP 1
#define CLK_PIX_GDP1 2
#define CLK_PIX_GDP2 3
#define CLK_PIX_GDP3 4
#define CLK_PIX_GDP4 5
#define CLK_PIX_AUX_DISP 6
#define CLK_DENC 7
#define CLK_PIX_HDDAC 8
#define CLK_HDDAC 9
#define CLK_SDDAC 10
#define CLK_PIX_DVO 11
#define CLK_DVO 12
#define CLK_PIX_HDMI 13
#define CLK_TMDS_HDMI 14
#define CLK_REF_HDMIPHY 15
/* CLOCKGEN D3 */
#define CLK_STFE_FRC1 0
#define CLK_TSOUT_0 1
#define CLK_TSOUT_1 2
#define CLK_MCHI 3
#define CLK_VSENS_COMPO 4
#define CLK_FRC1_REMOTE 5
#define CLK_LPC_0 6
#define CLK_LPC_1 7
#endif

61
include/dt-bindings/reset-controller/stih407-resets.h Normal file
View File

@ -0,0 +1,61 @@
/*
* This header provides constants for the reset controller
* based peripheral powerdown requests on the STMicroelectronics
* STiH407 SoC.
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
/* Powerdown requests control 0 */
#define STIH407_EMISS_POWERDOWN 0
#define STIH407_NAND_POWERDOWN 1
/* Synp GMAC PowerDown */
#define STIH407_ETH1_POWERDOWN 2
/* Powerdown requests control 1 */
#define STIH407_USB3_POWERDOWN 3
#define STIH407_USB2_PORT1_POWERDOWN 4
#define STIH407_USB2_PORT0_POWERDOWN 5
#define STIH407_PCIE1_POWERDOWN 6
#define STIH407_PCIE0_POWERDOWN 7
#define STIH407_SATA1_POWERDOWN 8
#define STIH407_SATA0_POWERDOWN 9
/* Reset defines */
#define STIH407_ETH1_SOFTRESET 0
#define STIH407_MMC1_SOFTRESET 1
#define STIH407_PICOPHY_SOFTRESET 2
#define STIH407_IRB_SOFTRESET 3
#define STIH407_PCIE0_SOFTRESET 4
#define STIH407_PCIE1_SOFTRESET 5
#define STIH407_SATA0_SOFTRESET 6
#define STIH407_SATA1_SOFTRESET 7
#define STIH407_MIPHY0_SOFTRESET 8
#define STIH407_MIPHY1_SOFTRESET 9
#define STIH407_MIPHY2_SOFTRESET 10
#define STIH407_SATA0_PWR_SOFTRESET 11
#define STIH407_SATA1_PWR_SOFTRESET 12
#define STIH407_DELTA_SOFTRESET 13
#define STIH407_BLITTER_SOFTRESET 14
#define STIH407_HDTVOUT_SOFTRESET 15
#define STIH407_HDQVDP_SOFTRESET 16
#define STIH407_VDP_AUX_SOFTRESET 17
#define STIH407_COMPO_SOFTRESET 18
#define STIH407_HDMI_TX_PHY_SOFTRESET 19
#define STIH407_JPEG_DEC_SOFTRESET 20
#define STIH407_VP8_DEC_SOFTRESET 21
#define STIH407_GPU_SOFTRESET 22
#define STIH407_HVA_SOFTRESET 23
#define STIH407_ERAM_HVA_SOFTRESET 24
#define STIH407_LPM_SOFTRESET 25
#define STIH407_KEYSCAN_SOFTRESET 26
#define STIH407_USB2_PORT0_SOFTRESET 27
#define STIH407_USB2_PORT1_SOFTRESET 28
/* Picophy reset defines */
#define STIH407_PICOPHY0_RESET 0
#define STIH407_PICOPHY1_RESET 1
#define STIH407_PICOPHY2_RESET 2
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */