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drm/i915: Ensure the HW is powered during display pipe HW readout 

The assumption when adding the intel_display_power_is_enabled() checks
was that if it returns success the power can't be turned off afterwards
during the HW access, which is guaranteed by modeset locks. This isn't
always true, so make sure we hold a dedicated reference for the time of
the access.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Revieved-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-3-git-send-email-imre.deak@intel.com
This commit is contained in:
Imre Deak 2016-02-12 18:55:11 +02:00
parent 0973128002
commit 1729050eb4
1 changed files with 48 additions and 19 deletions
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67
drivers/gpu/drm/i915/intel_display.c
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@ -8142,18 +8142,22 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
{ {
struct drm_device *dev = crtc->base.dev; struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
enum intel_display_power_domain power_domain;
uint32_t tmp; uint32_t tmp;
bool ret;
if (!intel_display_power_is_enabled(dev_priv, power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
POWER_DOMAIN_PIPE(crtc->pipe))) if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
return false; return false;
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = DPLL_ID_PRIVATE; pipe_config->shared_dpll = DPLL_ID_PRIVATE;
ret = false;
tmp = I915_READ(PIPECONF(crtc->pipe)); tmp = I915_READ(PIPECONF(crtc->pipe));
if (!(tmp & PIPECONF_ENABLE)) if (!(tmp & PIPECONF_ENABLE))
return false; goto out;
if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
switch (tmp & PIPECONF_BPC_MASK) { switch (tmp & PIPECONF_BPC_MASK) {
@ -8233,7 +8237,12 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->base.adjusted_mode.crtc_clock = pipe_config->base.adjusted_mode.crtc_clock =
pipe_config->port_clock / pipe_config->pixel_multiplier; pipe_config->port_clock / pipe_config->pixel_multiplier;
return true; ret = true;
out:
intel_display_power_put(dev_priv, power_domain);
return ret;
} }
static void ironlake_init_pch_refclk(struct drm_device *dev) static void ironlake_init_pch_refclk(struct drm_device *dev)
@ -9337,18 +9346,21 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
{ {
struct drm_device *dev = crtc->base.dev; struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
enum intel_display_power_domain power_domain;
uint32_t tmp; uint32_t tmp;
bool ret;
if (!intel_display_power_is_enabled(dev_priv, power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
POWER_DOMAIN_PIPE(crtc->pipe))) if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
return false; return false;
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = DPLL_ID_PRIVATE; pipe_config->shared_dpll = DPLL_ID_PRIVATE;
ret = false;
tmp = I915_READ(PIPECONF(crtc->pipe)); tmp = I915_READ(PIPECONF(crtc->pipe));
if (!(tmp & PIPECONF_ENABLE)) if (!(tmp & PIPECONF_ENABLE))
return false; goto out;
switch (tmp & PIPECONF_BPC_MASK) { switch (tmp & PIPECONF_BPC_MASK) {
case PIPECONF_6BPC: case PIPECONF_6BPC:
@ -9411,7 +9423,12 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
ironlake_get_pfit_config(crtc, pipe_config); ironlake_get_pfit_config(crtc, pipe_config);
return true; ret = true;
out:
intel_display_power_put(dev_priv, power_domain);
return ret;
} }
static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
@ -9940,12 +9957,17 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
{ {
struct drm_device *dev = crtc->base.dev; struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
enum intel_display_power_domain pfit_domain; enum intel_display_power_domain power_domain;
unsigned long power_domain_mask;
uint32_t tmp; uint32_t tmp;
bool ret;
if (!intel_display_power_is_enabled(dev_priv, power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
POWER_DOMAIN_PIPE(crtc->pipe))) if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
return false; return false;
power_domain_mask = BIT(power_domain);
ret = false;
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = DPLL_ID_PRIVATE; pipe_config->shared_dpll = DPLL_ID_PRIVATE;
@ -9972,13 +9994,14 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
pipe_config->cpu_transcoder = TRANSCODER_EDP; pipe_config->cpu_transcoder = TRANSCODER_EDP;
} }
if (!intel_display_power_is_enabled(dev_priv, power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
return false; goto out;
power_domain_mask |= BIT(power_domain);
tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
if (!(tmp & PIPECONF_ENABLE)) if (!(tmp & PIPECONF_ENABLE))
return false; goto out;
haswell_get_ddi_port_state(crtc, pipe_config); haswell_get_ddi_port_state(crtc, pipe_config);
@ -9988,14 +10011,14 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
skl_init_scalers(dev, crtc, pipe_config); skl_init_scalers(dev, crtc, pipe_config);
} }
pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
if (INTEL_INFO(dev)->gen >= 9) { if (INTEL_INFO(dev)->gen >= 9) {
pipe_config->scaler_state.scaler_id = -1; pipe_config->scaler_state.scaler_id = -1;
pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
} }
if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
power_domain_mask |= BIT(power_domain);
if (INTEL_INFO(dev)->gen >= 9) if (INTEL_INFO(dev)->gen >= 9)
skylake_get_pfit_config(crtc, pipe_config); skylake_get_pfit_config(crtc, pipe_config);
else else
@ -10013,7 +10036,13 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier = 1; pipe_config->pixel_multiplier = 1;
} }
return true; ret = true;
out:
for_each_power_domain(power_domain, power_domain_mask)
intel_display_power_put(dev_priv, power_domain);
return ret;
} }
static void i845_update_cursor(struct drm_crtc *crtc, u32 base, static void i845_update_cursor(struct drm_crtc *crtc, u32 base,