gpio: zynq: Fix driver function parameters alignment
Fix function parameters alignment reported by checkpatch. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -194,7 +194,7 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
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for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
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if ((pin_num >= gpio->p_data->bank_min[bank]) &&
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(pin_num <= gpio->p_data->bank_max[bank])) {
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(pin_num <= gpio->p_data->bank_max[bank])) {
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*bank_num = bank;
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*bank_pin_num = pin_num -
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gpio->p_data->bank_min[bank];
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@ -310,7 +310,7 @@ static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
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* as inputs.
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*/
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if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
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(bank_pin_num == 7 || bank_pin_num == 8))
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(bank_pin_num == 7 || bank_pin_num == 8))
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return -EINVAL;
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/* clear the bit in direction mode reg to set the pin as input */
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@ -511,13 +511,14 @@ static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
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writel_relaxed(int_any,
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gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
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if (type & IRQ_TYPE_LEVEL_MASK) {
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if (type & IRQ_TYPE_LEVEL_MASK)
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irq_set_chip_handler_name_locked(irq_data,
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&zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
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} else {
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&zynq_gpio_level_irqchip,
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handle_fasteoi_irq, NULL);
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else
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irq_set_chip_handler_name_locked(irq_data,
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&zynq_gpio_edge_irqchip, handle_level_irq, NULL);
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}
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&zynq_gpio_edge_irqchip,
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handle_level_irq, NULL);
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return 0;
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}
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@ -733,7 +734,7 @@ static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
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static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
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SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
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zynq_gpio_runtime_resume, NULL)
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zynq_gpio_runtime_resume, NULL)
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};
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static const struct zynq_platform_data zynqmp_gpio_def = {
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