ARM: tegra: Define Tegra114 CAR binding
The device tree binding models Tegra114 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver
Stephen Warren
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NVIDIA Tegra114 Clock And Reset Controller
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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for muxing and gating Tegra's clocks, and setting their rates.
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Required properties :
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- compatible : Should be "nvidia,tegra114-car"
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- reg : Should contain CAR registers location and length
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- clocks : Should contain phandle and clock specifiers for two clocks:
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the 32 KHz "32k_in", and the board-specific oscillator "osc".
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- #clock-cells : Should be 1.
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In clock consumers, this cell represents the clock ID exposed by the CAR.
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The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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registers. These IDs often match those in the CAR's RST_DEVICES registers,
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but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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this case, those clocks are assigned IDs above 160 in order to highlight
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this issue. Implementations that interpret these clock IDs as bit values
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within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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explicitly handle these special cases.
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The balance of the clocks controlled by the CAR are assigned IDs of 160 and
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above.
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0 unassigned
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1 unassigned
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2 unassigned
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3 unassigned
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4 rtc
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5 timer
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6 uarta
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7 unassigned (register bit affects uartb and vfir)
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8 unassigned
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9 sdmmc2
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10 unassigned (register bit affects spdif_in and spdif_out)
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11 i2s1
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12 i2c1
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13 ndflash
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14 sdmmc1
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15 sdmmc4
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16 unassigned
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17 pwm
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18 i2s2
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19 epp
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20 unassigned (register bit affects vi and vi_sensor)
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21 2d
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22 usbd
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23 isp
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24 3d
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25 unassigned
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26 disp2
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27 disp1
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28 host1x
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29 vcp
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30 i2s0
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31 unassigned
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32 unassigned
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33 unassigned
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34 apbdma
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35 unassigned
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36 kbc
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37 unassigned
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38 unassigned
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39 unassigned (register bit affects fuse and fuse_burn)
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40 kfuse
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41 sbc1
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42 nor
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43 unassigned
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44 sbc2
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45 unassigned
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46 sbc3
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47 i2c5
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48 dsia
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49 unassigned
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50 mipi
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51 hdmi
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52 csi
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53 unassigned
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54 i2c2
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55 uartc
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56 mipi-cal
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57 emc
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58 usb2
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59 usb3
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60 msenc
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61 vde
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62 bsea
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63 bsev
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64 unassigned
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65 uartd
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66 unassigned
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67 i2c3
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68 sbc4
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69 sdmmc3
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70 unassigned
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71 owr
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72 afi
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73 csite
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74 unassigned
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75 unassigned
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76 la
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77 trace
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78 soc_therm
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79 dtv
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80 ndspeed
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81 i2cslow
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82 dsib
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83 tsec
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84 unassigned
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85 unassigned
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86 unassigned
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87 unassigned
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88 unassigned
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89 xusb_host
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90 unassigned
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91 msenc
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92 csus
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93 unassigned
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94 unassigned
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95 unassigned (bit affects xusb_dev and xusb_dev_src)
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96 unassigned
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97 unassigned
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98 unassigned
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99 mselect
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100 tsensor
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101 i2s3
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102 i2s4
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103 i2c4
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104 sbc5
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105 sbc6
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106 d_audio
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107 apbif
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108 dam0
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109 dam1
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110 dam2
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111 hda2codec_2x
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112 unassigned
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113 audio0_2x
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114 audio1_2x
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115 audio2_2x
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116 audio3_2x
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117 audio4_2x
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118 spdif_2x
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119 actmon
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120 extern1
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121 extern2
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122 extern3
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123 unassigned
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124 unassigned
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125 hda
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126 unassigned
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127 se
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128 hda2hdmi
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129 unassigned
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130 unassigned
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131 unassigned
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132 unassigned
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133 unassigned
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134 unassigned
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135 unassigned
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136 unassigned
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137 unassigned
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138 unassigned
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139 unassigned
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140 unassigned
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141 unassigned
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142 unassigned
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143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
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xusb_host_src and xusb_ss_src)
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144 cilab
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145 cilcd
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146 cile
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147 dsialp
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148 dsiblp
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149 unassigned
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150 dds
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151 unassigned
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152 dp2
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153 amx
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154 adx
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155 unassigned (bit affects dfll_ref and dfll_soc)
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156 xusb_ss
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192 uartb
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193 vfir
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194 spdif_in
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195 spdif_out
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196 vi
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197 vi_sensor
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198 fuse
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199 fuse_burn
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200 clk_32k
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201 clk_m
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202 clk_m_div2
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203 clk_m_div4
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204 pll_ref
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205 pll_c
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206 pll_c_out1
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207 pll_c2
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208 pll_c3
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209 pll_m
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210 pll_m_out1
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211 pll_p
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212 pll_p_out1
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213 pll_p_out2
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214 pll_p_out3
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215 pll_p_out4
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216 pll_a
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217 pll_a_out0
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218 pll_d
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219 pll_d_out0
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220 pll_d2
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221 pll_d2_out0
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222 pll_u
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223 pll_u_480M
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224 pll_u_60M
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225 pll_u_48M
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226 pll_u_12M
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227 pll_x
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228 pll_x_out0
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229 pll_re_vco
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230 pll_re_out
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231 pll_e_out0
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232 spdif_in_sync
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233 i2s0_sync
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234 i2s1_sync
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235 i2s2_sync
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236 i2s3_sync
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237 i2s4_sync
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238 vimclk_sync
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239 audio0
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240 audio1
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241 audio2
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242 audio3
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243 audio4
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244 spdif
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245 clk_out_1
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246 clk_out_2
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247 clk_out_3
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248 blink
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252 xusb_host_src
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253 xusb_falcon_src
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254 xusb_fs_src
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255 xusb_ss_src
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256 xusb_dev_src
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257 xusb_dev
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258 xusb_hs_src
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259 sclk
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260 hclk
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261 pclk
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262 cclk_g
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263 cclk_lp
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264 dfll_ref
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265 dfll_soc
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Example SoC include file:
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/ {
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tegra_car: clock {
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compatible = "nvidia,tegra114-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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usb@c5004000 {
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clocks = <&tegra_car 58>; /* usb2 */
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};
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};
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Example board file:
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/ {
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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osc: clock@0 {
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compatible = "fixed-clock";
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reg = <0>;
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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clk_32k: clock@1 {
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compatible = "fixed-clock";
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reg = <1>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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&tegra_car {
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clocks = <&clk_32k> <&osc>;
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};
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};
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