drm/nv50/disp: handle multiple actions from one set of supervisor intrs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
a91ed42de2
commit
16d4c031dd
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@ -972,21 +972,29 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
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}
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static void
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nv50_disp_intr_unk10(struct nv50_disp_priv *priv, u32 super)
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nv50_disp_intr_unk10_0(struct nv50_disp_priv *priv, int head)
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{
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int head = ffs((super & 0x00000060) >> 5) - 1;
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if (head >= 0) {
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head = ffs((super & 0x00000180) >> 7) - 1;
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if (head >= 0)
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exec_script(priv, head, 1);
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}
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nv_wr32(priv, 0x610030, 0x80000000);
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exec_script(priv, head, 1);
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}
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static void
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nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv,
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struct dcb_output *outp, u32 pclk)
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nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head)
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{
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exec_script(priv, head, 2);
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}
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static void
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nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head)
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{
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struct nouveau_clock *clk = nouveau_clock(priv);
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u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
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if (pclk)
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clk->pll_set(clk, PLL_VPLL0 + head, pclk);
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}
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static void
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nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv,
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struct dcb_output *outp, u32 pclk)
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{
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const int link = !(outp->sorconf.link & 1);
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const int or = ffs(outp->or) - 1;
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@ -1092,77 +1100,54 @@ nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv,
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}
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static void
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nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
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nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
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{
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struct dcb_output outp;
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int head;
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u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
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u32 hval, hreg = 0x614200 + (head * 0x800);
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u32 oval, oreg;
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u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
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if (conf != ~0) {
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if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
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u32 soff = (ffs(outp.or) - 1) * 0x08;
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u32 ctrl = nv_rd32(priv, 0x610798 + soff);
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u32 datarate;
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/* finish detaching encoder? */
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head = ffs((super & 0x00000180) >> 7) - 1;
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if (head >= 0)
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exec_script(priv, head, 2);
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/* check whether a vpll change is required */
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head = ffs((super & 0x00000600) >> 9) - 1;
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if (head >= 0) {
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u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
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if (pclk) {
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struct nouveau_clock *clk = nouveau_clock(priv);
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clk->pll_set(clk, PLL_VPLL0 + head, pclk);
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}
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}
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/* (re)attach the relevant OR to the head */
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head = ffs((super & 0x00000180) >> 7) - 1;
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if (head >= 0) {
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u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
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u32 hval, hreg = 0x614200 + (head * 0x800);
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u32 oval, oreg;
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u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
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if (conf != ~0) {
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if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
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u32 soff = (ffs(outp.or) - 1) * 0x08;
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u32 ctrl = nv_rd32(priv, 0x610798 + soff);
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u32 datarate;
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switch ((ctrl & 0x000f0000) >> 16) {
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case 6: datarate = pclk * 30 / 8; break;
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case 5: datarate = pclk * 24 / 8; break;
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case 2:
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default:
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datarate = pclk * 18 / 8;
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break;
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}
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nouveau_dp_train(&priv->base, priv->sor.dp,
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&outp, head, datarate);
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switch ((ctrl & 0x000f0000) >> 16) {
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case 6: datarate = pclk * 30 / 8; break;
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case 5: datarate = pclk * 24 / 8; break;
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case 2:
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default:
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datarate = pclk * 18 / 8;
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break;
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}
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exec_clkcmp(priv, head, 0, pclk, &outp);
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if (!outp.location && outp.type == DCB_OUTPUT_ANALOG) {
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oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;
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oval = 0x00000000;
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hval = 0x00000000;
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} else
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if (!outp.location) {
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if (outp.type == DCB_OUTPUT_DP)
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nv50_disp_intr_unk20_dp(priv, &outp, pclk);
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oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;
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oval = (conf & 0x0100) ? 0x0101 : 0x0000;
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hval = 0x00000000;
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} else {
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oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;
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oval = 0x00000001;
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hval = 0x00000001;
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}
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nv_mask(priv, hreg, 0x0000000f, hval);
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nv_mask(priv, oreg, 0x00000707, oval);
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nouveau_dp_train(&priv->base, priv->sor.dp,
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&outp, head, datarate);
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}
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}
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nv_wr32(priv, 0x610030, 0x80000000);
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exec_clkcmp(priv, head, 0, pclk, &outp);
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if (!outp.location && outp.type == DCB_OUTPUT_ANALOG) {
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oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;
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oval = 0x00000000;
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hval = 0x00000000;
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} else
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if (!outp.location) {
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if (outp.type == DCB_OUTPUT_DP)
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nv50_disp_intr_unk20_2_dp(priv, &outp, pclk);
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oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;
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oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
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hval = 0x00000000;
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} else {
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oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;
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oval = 0x00000001;
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hval = 0x00000001;
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}
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nv_mask(priv, hreg, 0x0000000f, hval);
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nv_mask(priv, oreg, 0x00000707, oval);
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}
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}
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/* If programming a TMDS output on a SOR that can also be configured for
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@ -1174,7 +1159,7 @@ nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
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* programmed for DisplayPort.
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*/
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static void
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nv50_disp_intr_unk40_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
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nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
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{
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struct nouveau_bios *bios = nouveau_bios(priv);
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const int link = !(outp->sorconf.link & 1);
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@ -1188,37 +1173,32 @@ nv50_disp_intr_unk40_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
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}
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static void
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nv50_disp_intr_unk40(struct nv50_disp_priv *priv, u32 super)
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nv50_disp_intr_unk40_0(struct nv50_disp_priv *priv, int head)
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{
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int head = ffs((super & 0x00000180) >> 7) - 1;
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if (head >= 0) {
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struct dcb_output outp;
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u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
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if (exec_clkcmp(priv, head, 1, pclk, &outp) != ~0) {
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if (outp.location == 0 && outp.type == DCB_OUTPUT_TMDS)
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nv50_disp_intr_unk40_tmds(priv, &outp);
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else
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if (outp.location == 1 && outp.type == DCB_OUTPUT_DP) {
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u32 soff = (ffs(outp.or) - 1) * 0x08;
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u32 ctrl = nv_rd32(priv, 0x610b84 + soff);
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u32 datarate;
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struct dcb_output outp;
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u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
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if (exec_clkcmp(priv, head, 1, pclk, &outp) != ~0) {
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if (outp.location == 0 && outp.type == DCB_OUTPUT_TMDS)
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nv50_disp_intr_unk40_0_tmds(priv, &outp);
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else
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if (outp.location == 1 && outp.type == DCB_OUTPUT_DP) {
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u32 soff = (ffs(outp.or) - 1) * 0x08;
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u32 ctrl = nv_rd32(priv, 0x610b84 + soff);
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u32 datarate;
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switch ((ctrl & 0x000f0000) >> 16) {
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case 6: datarate = pclk * 30 / 8; break;
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case 5: datarate = pclk * 24 / 8; break;
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case 2:
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default:
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datarate = pclk * 18 / 8;
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break;
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}
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nouveau_dp_train(&priv->base, priv->pior.dp,
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&outp, head, datarate);
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switch ((ctrl & 0x000f0000) >> 16) {
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case 6: datarate = pclk * 30 / 8; break;
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case 5: datarate = pclk * 24 / 8; break;
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case 2:
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default:
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datarate = pclk * 18 / 8;
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break;
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}
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nouveau_dp_train(&priv->base, priv->pior.dp,
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&outp, head, datarate);
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}
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}
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nv_wr32(priv, 0x610030, 0x80000000);
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}
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void
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@ -1227,15 +1207,45 @@ nv50_disp_intr_supervisor(struct work_struct *work)
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struct nv50_disp_priv *priv =
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container_of(work, struct nv50_disp_priv, supervisor);
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u32 super = nv_rd32(priv, 0x610030);
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int head;
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nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super);
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if (priv->super & 0x00000010)
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nv50_disp_intr_unk10(priv, super);
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if (priv->super & 0x00000020)
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nv50_disp_intr_unk20(priv, super);
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if (priv->super & 0x00000040)
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nv50_disp_intr_unk40(priv, super);
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if (priv->super & 0x00000010) {
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for (head = 0; head < priv->head.nr; head++) {
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if (!(super & (0x00000020 << head)))
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continue;
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if (!(super & (0x00000080 << head)))
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continue;
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nv50_disp_intr_unk10_0(priv, head);
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}
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} else
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if (priv->super & 0x00000020) {
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for (head = 0; head < priv->head.nr; head++) {
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if (!(super & (0x00000080 << head)))
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continue;
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nv50_disp_intr_unk20_0(priv, head);
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}
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for (head = 0; head < priv->head.nr; head++) {
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if (!(super & (0x00000200 << head)))
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continue;
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nv50_disp_intr_unk20_1(priv, head);
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}
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for (head = 0; head < priv->head.nr; head++) {
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if (!(super & (0x00000080 << head)))
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continue;
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nv50_disp_intr_unk20_2(priv, head);
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}
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} else
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if (priv->super & 0x00000040) {
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for (head = 0; head < priv->head.nr; head++) {
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if (!(super & (0x00000080 << head)))
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continue;
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nv50_disp_intr_unk40_0(priv, head);
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}
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}
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nv_wr32(priv, 0x610030, 0x80000000);
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}
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void
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