drm/amd/display: Allow dmu_stg to support cached inbox for dmub

[Why]
FW version check doesn't allow dmu_stg to support cached inbox,
which yields much better performance than region 4.

[How]
Check a range of fw versions, rather than a simple greater than check.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wyatt Wood 2020-12-03 22:04:27 -05:00 committed by Alex Deucher
parent 69d5c7f398
commit 16ca2d465d
1 changed files with 9 additions and 2 deletions

View File

@ -81,6 +81,13 @@ static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
}
static inline bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)
{
/* Cached inbox is not supported in this fw version range */
return !(dmub->fw_version >= DMUB_FW_VERSION(1, 0, 0) &&
dmub->fw_version <= DMUB_FW_VERSION(1, 10, 0));
}
void dmub_dcn20_reset(struct dmub_srv *dmub)
{
union dmub_gpint_data_register cmd;
@ -216,7 +223,7 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
/* New firmware can support CW4. */
if (dmub->fw_version > DMUB_FW_VERSION(1, 0, 10)) {
if (dmub_dcn20_use_cached_inbox(dmub)) {
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
@ -255,7 +262,7 @@ void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
const struct dmub_region *inbox1)
{
/* New firmware can support CW4 for the inbox. */
if (dmub->fw_version > DMUB_FW_VERSION(1, 0, 10))
if (dmub_dcn20_use_cached_inbox(dmub))
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
else
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);