pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pins
Update the R-Car M3-W pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M3-W SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
This commit is contained in:
Geert Uytterhoeven
parent
42ee6c3395
commit
168e18fd6c
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@ -32,6 +32,51 @@
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PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
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#define CPU_ALL_NOGP(fn) \
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PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
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PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
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/*
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* F_() : just information
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* FM() : macro for FN_xxx / xxx_MARK
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@ -1510,66 +1555,16 @@ static const u16 pinmux_data[] = {
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};
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/*
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* R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
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* Physical layout rows: A - AW, cols: 1 - 39.
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* Pins not associated with a GPIO port.
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*/
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#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
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#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
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#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
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enum {
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GP_ASSIGN_LAST(),
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NOGP_ALL(),
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};
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static const struct sh_pfc_pin pinmux_pins[] = {
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PINMUX_GPIO_GP_ALL(),
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/*
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* Pins not associated with a GPIO port.
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*
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* The pin positions are different between different r8a7796
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* packages, all that is needed for the pfc driver is a unique
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* number for each pin. To this end use the pin layout from
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* R-Car M3SiP to calculate a unique number for each pin.
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*/
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SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP_DOWN),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP_DOWN),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP_DOWN),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP_DOWN),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
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PINMUX_NOGP_ALL(),
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};
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/* - AUDIO CLOCK ------------------------------------------------------------ */
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@ -1718,7 +1713,7 @@ static const unsigned int avb_phy_int_mux[] = {
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};
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static const unsigned int avb_mdio_pins[] = {
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/* AVB_MDC, AVB_MDIO */
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RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
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RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
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};
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static const unsigned int avb_mdio_mux[] = {
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AVB_MDC_MARK, AVB_MDIO_MARK,
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@ -1731,11 +1726,11 @@ static const unsigned int avb_mii_pins[] = {
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* AVB_RD1, AVB_RD2, AVB_RD3,
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* AVB_TXCREFCLK
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*/
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PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
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PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
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PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
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PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
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PIN_NUMBER('A', 12),
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PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
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PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
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PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
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PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
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PIN_AVB_TXCREFCLK,
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};
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static const unsigned int avb_mii_mux[] = {
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@ -5629,44 +5624,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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static const struct pinmux_drive_reg pinmux_drive_regs[] = {
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{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
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{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
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{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
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{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
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{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
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{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
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{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
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{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
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{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
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{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
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{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
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{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
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{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
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{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
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{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
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{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
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{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
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} },
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{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
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{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
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{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
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{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
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{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
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{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
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{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
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{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
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{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
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{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
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{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
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{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
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{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
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{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
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{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
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{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
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{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
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} },
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{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
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{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
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{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
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{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
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{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
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{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
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{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
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{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
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{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
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{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
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{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
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{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
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{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
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{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
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{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
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{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
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{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
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} },
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{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
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{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
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{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
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{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
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{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
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{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
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{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
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{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
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{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
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{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
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{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
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{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
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{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
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{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
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{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
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{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
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{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
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} },
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{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
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{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
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@ -5720,7 +5715,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
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} },
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{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
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{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
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{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
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{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
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{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
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{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
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{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
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@ -5739,29 +5734,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
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{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
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} },
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{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
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{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
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{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
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{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
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{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
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{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
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{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
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{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
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{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
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{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
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{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
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{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
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{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
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{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
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{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
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{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
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{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
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} },
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{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
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{ PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
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{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
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{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
|
||||
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
|
||||
{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */
|
||||
{ PIN_TMS, 4, 2 }, /* TMS */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
|
||||
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
|
||||
{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
|
||||
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
|
||||
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
|
||||
{ PIN_TDO, 28, 2 }, /* TDO */
|
||||
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
|
||||
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
|
||||
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
|
||||
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
|
||||
|
|
@ -5830,7 +5825,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
|
||||
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
|
||||
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
|
||||
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
|
||||
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
|
||||
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
|
||||
|
|
@ -5903,35 +5898,35 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
|
|||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
|
||||
[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
|
||||
[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
|
||||
[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
|
||||
[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
|
||||
[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
|
||||
[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
|
||||
[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
|
||||
[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
|
||||
[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
|
||||
[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
|
||||
[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
|
||||
[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
|
||||
[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
|
||||
[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
|
||||
[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
|
||||
[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
|
||||
[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
|
||||
[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
|
||||
[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
|
||||
[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
|
||||
[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
|
||||
[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
|
||||
[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
|
||||
[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
|
||||
[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
|
||||
[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
|
||||
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
|
||||
[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
|
||||
[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
|
||||
[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
|
||||
[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
|
||||
[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
|
||||
[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
|
||||
[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
|
||||
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
|
||||
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
|
||||
[12] = PIN_RPC_INT_N, /* RPC_INT# */
|
||||
[13] = PIN_RPC_WP_N, /* RPC_WP# */
|
||||
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
|
||||
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
|
||||
[16] = PIN_AVB_RXC, /* AVB_RXC */
|
||||
[17] = PIN_AVB_RD0, /* AVB_RD0 */
|
||||
[18] = PIN_AVB_RD1, /* AVB_RD1 */
|
||||
[19] = PIN_AVB_RD2, /* AVB_RD2 */
|
||||
[20] = PIN_AVB_RD3, /* AVB_RD3 */
|
||||
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
|
||||
[22] = PIN_AVB_TXC, /* AVB_TXC */
|
||||
[23] = PIN_AVB_TD0, /* AVB_TD0 */
|
||||
[24] = PIN_AVB_TD1, /* AVB_TD1 */
|
||||
[25] = PIN_AVB_TD2, /* AVB_TD2 */
|
||||
[26] = PIN_AVB_TD3, /* AVB_TD3 */
|
||||
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
|
||||
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
|
||||
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
|
||||
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
|
||||
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
|
||||
|
|
@ -5980,7 +5975,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
|
||||
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
|
||||
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
|
||||
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
|
||||
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[10] = RCAR_GP_PIN(0, 0), /* D0 */
|
||||
[11] = RCAR_GP_PIN(0, 1), /* D1 */
|
||||
[12] = RCAR_GP_PIN(0, 2), /* D2 */
|
||||
|
|
@ -6001,20 +5996,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
|
||||
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
|
||||
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
|
||||
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
|
||||
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
|
||||
[ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
|
||||
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
|
||||
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
|
||||
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
|
||||
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
|
||||
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
|
||||
[ 2] = PIN_FSCLKST, /* FSCLKST */
|
||||
[ 3] = PIN_EXTALR, /* EXTALR*/
|
||||
[ 4] = PIN_TRST_N, /* TRST# */
|
||||
[ 5] = PIN_TCK, /* TCK */
|
||||
[ 6] = PIN_TMS, /* TMS */
|
||||
[ 7] = PIN_TDI, /* TDI */
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
|
||||
[ 9] = PIN_ASEBRK, /* ASEBRK */
|
||||
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
|
||||
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
|
||||
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
|
||||
|
|
@ -6079,7 +6074,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
|
||||
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
|
||||
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
|
||||
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
|
||||
[ 6] = PIN_MLB_REF, /* MLB_REF */
|
||||
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
|
||||
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
|
||||
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue