x86, acpi, idle: Restructure the mwait idle routines
People seem to delight in writing wrong and broken mwait idle routines; collapse the lot. This leaves mwait_play_dead() the sole remaining user of __mwait() and new __mwait() users are probably doing it wrong. Also remove __sti_mwait() as its unused. Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Jacob Jun Pan <jacob.jun.pan@linux.intel.com> Cc: Mike Galbraith <bitbucket@online.de> Cc: Len Brown <lenb@kernel.org> Cc: Rui Zhang <rui.zhang@intel.com> Acked-by: Rafael Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/20131212141654.616820819@infradead.org Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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1682425539
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@ -1,6 +1,8 @@
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#ifndef _ASM_X86_MWAIT_H
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#define _ASM_X86_MWAIT_H
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#include <linux/sched.h>
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#define MWAIT_SUBSTATE_MASK 0xf
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#define MWAIT_CSTATE_MASK 0xf
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#define MWAIT_SUBSTATE_SIZE 4
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@ -13,4 +15,42 @@
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#define MWAIT_ECX_INTERRUPT_BREAK 0x1
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static inline void __monitor(const void *eax, unsigned long ecx,
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unsigned long edx)
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{
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/* "monitor %eax, %ecx, %edx;" */
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asm volatile(".byte 0x0f, 0x01, 0xc8;"
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:: "a" (eax), "c" (ecx), "d"(edx));
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}
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static inline void __mwait(unsigned long eax, unsigned long ecx)
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{
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/* "mwait %eax, %ecx;" */
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asm volatile(".byte 0x0f, 0x01, 0xc9;"
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:: "a" (eax), "c" (ecx));
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}
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/*
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* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
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* which can obviate IPI to trigger checking of need_resched.
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* We execute MONITOR against need_resched and enter optimized wait state
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* through MWAIT. Whenever someone changes need_resched, we would be woken
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* up from MWAIT (without an IPI).
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*
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* New with Core Duo processors, MWAIT can take some hints based on CPU
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* capability.
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*/
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static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
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{
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if (!current_set_polling_and_test()) {
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if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
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clflush((void *)¤t_thread_info()->flags);
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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if (!need_resched())
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__mwait(eax, ecx);
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}
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__current_clr_polling();
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}
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#endif /* _ASM_X86_MWAIT_H */
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@ -700,29 +700,6 @@ static inline void sync_core(void)
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#endif
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}
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static inline void __monitor(const void *eax, unsigned long ecx,
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unsigned long edx)
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{
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/* "monitor %eax, %ecx, %edx;" */
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asm volatile(".byte 0x0f, 0x01, 0xc8;"
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:: "a" (eax), "c" (ecx), "d"(edx));
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}
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static inline void __mwait(unsigned long eax, unsigned long ecx)
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{
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/* "mwait %eax, %ecx;" */
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asm volatile(".byte 0x0f, 0x01, 0xc9;"
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:: "a" (eax), "c" (ecx));
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}
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static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
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{
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trace_hardirqs_on();
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/* "mwait %eax, %ecx;" */
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asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
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:: "a" (eax), "c" (ecx));
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}
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extern void select_idle_routine(const struct cpuinfo_x86 *c);
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extern void init_amd_e400_c1e_mask(void);
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@ -150,29 +150,6 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu,
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}
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EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
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/*
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* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
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* which can obviate IPI to trigger checking of need_resched.
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* We execute MONITOR against need_resched and enter optimized wait state
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* through MWAIT. Whenever someone changes need_resched, we would be woken
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* up from MWAIT (without an IPI).
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*
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* New with Core Duo processors, MWAIT can take some hints based on CPU
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* capability.
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*/
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void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
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{
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if (!need_resched()) {
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if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
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clflush((void *)¤t_thread_info()->flags);
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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smp_mb();
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if (!need_resched())
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__mwait(ax, cx);
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}
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}
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void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
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{
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unsigned int cpu = smp_processor_id();
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@ -193,10 +193,7 @@ static int power_saving_thread(void *data)
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CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
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stop_critical_timings();
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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smp_mb();
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if (!need_resched())
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__mwait(power_saving_mwait_eax, 1);
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mwait_idle_with_hints(power_saving_mwait_eax, 1);
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start_critical_timings();
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if (lapic_marked_unstable)
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@ -727,11 +727,6 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
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if (unlikely(!pr))
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return -EINVAL;
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if (cx->entry_method == ACPI_CSTATE_FFH) {
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if (current_set_polling_and_test())
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return -EINVAL;
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}
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lapic_timer_state_broadcast(pr, cx, 1);
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acpi_idle_do_entry(cx);
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@ -785,11 +780,6 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
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if (unlikely(!pr))
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return -EINVAL;
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if (cx->entry_method == ACPI_CSTATE_FFH) {
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if (current_set_polling_and_test())
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return -EINVAL;
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}
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/*
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* Must be done before busmaster disable as we might need to
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* access HPET !
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@ -841,11 +831,6 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
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}
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}
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if (cx->entry_method == ACPI_CSTATE_FFH) {
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if (current_set_polling_and_test())
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return -EINVAL;
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}
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acpi_unlazy_tlb(smp_processor_id());
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/* Tell the scheduler that we are going deep-idle: */
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@ -375,16 +375,7 @@ static int intel_idle(struct cpuidle_device *dev,
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if (!(lapic_timer_reliable_states & (1 << (cstate))))
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
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if (!current_set_polling_and_test()) {
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if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
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clflush((void *)¤t_thread_info()->flags);
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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smp_mb();
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if (!need_resched())
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__mwait(eax, ecx);
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}
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mwait_idle_with_hints(eax, ecx);
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if (!(lapic_timer_reliable_states & (1 << (cstate))))
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
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@ -438,9 +438,7 @@ static int clamp_thread(void *arg)
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*/
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local_touch_nmi();
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stop_critical_timings();
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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cpu_relax(); /* allow HT sibling to run */
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__mwait(eax, ecx);
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mwait_idle_with_hints(eax, ecx);
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start_critical_timings();
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atomic_inc(&idle_wakeup_counter);
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}
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