[ARM] MXC: add pwm driver for i.MX SoCs
This driver has been tested on MX27/MX31. It should work on MX1/MX1 aswell, but the actual setting of the PWM is missing so far. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
1512222b10
commit
166091b189
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@ -44,4 +44,10 @@ config MXC_IRQ_PRIOR
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requirements for timing.
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Say N here, unless you have a specialized requirement.
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config MXC_PWM
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tristate "Enable PWM driver"
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depends on ARCH_MXC
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help
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Enable support for the i.MX PWM controller(s).
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endif
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@ -7,3 +7,4 @@ obj-y := irq.o clock.o gpio.o time.o devices.o
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obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
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obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
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obj-$(CONFIG_MXC_PWM) += pwm.o
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@ -0,0 +1,300 @@
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/*
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* simple driver for PWM (Pulse Width Modulator) controller
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/pwm.h>
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#if defined CONFIG_ARCH_MX1 || defined CONFIG_ARCH_MX21
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#define PWM_VER_1
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#define PWMCR 0x00 /* PWM Control Register */
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#define PWMSR 0x04 /* PWM Sample Register */
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#define PWMPR 0x08 /* PWM Period Register */
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#define PWMCNR 0x0C /* PWM Counter Register */
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#define PWMCR_HCTR (1 << 18) /* Halfword FIFO Data Swapping */
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#define PWMCR_BCTR (1 << 17) /* Byte FIFO Data Swapping */
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#define PWMCR_SWR (1 << 16) /* Software Reset */
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#define PWMCR_CLKSRC_PERCLK (0 << 15) /* PERCLK Clock Source */
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#define PWMCR_CLKSRC_CLK32 (1 << 15) /* 32KHz Clock Source */
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#define PWMCR_PRESCALER(x) (((x - 1) & 0x7F) << 8) /* PRESCALER */
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#define PWMCR_IRQ (1 << 7) /* Interrupt Request */
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#define PWMCR_IRQEN (1 << 6) /* Interrupt Request Enable */
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#define PWMCR_FIFOAV (1 << 5) /* FIFO Available */
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#define PWMCR_EN (1 << 4) /* Enables/Disables the PWM */
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#define PWMCR_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */
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#define PWMCR_DIV(x) (((x) & 0x03) << 0) /* Clock divider 2/4/8/16 */
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#define MAX_DIV (128 * 16)
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#endif
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#if defined CONFIG_MACH_MX27 || defined CONFIG_ARCH_MX31
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#define PWM_VER_2
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#define PWMCR 0x00 /* PWM Control Register */
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#define PWMSR 0x04 /* PWM Status Register */
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#define PWMIR 0x08 /* PWM Interrupt Register */
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#define PWMSAR 0x0C /* PWM Sample Register */
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#define PWMPR 0x10 /* PWM Period Register */
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#define PWMCNR 0x14 /* PWM Counter Register */
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#define PWMCR_EN (1 << 0) /* Enables/Disables the PWM */
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#define PWMCR_REPEAT(x) (((x) & 0x03) << 1) /* Sample Repeats */
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#define PWMCR_SWR (1 << 3) /* Software Reset */
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#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)/* PRESCALER */
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#define PWMCR_CLKSRC(x) (((x) & 0x3) << 16)
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#define PWMCR_CLKSRC_OFF (0 << 16)
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#define PWMCR_CLKSRC_IPG (1 << 16)
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#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
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#define PWMCR_CLKSRC_CLK32 (3 << 16)
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#define PWMCR_POUTC
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#define PWMCR_HCTR (1 << 20) /* Halfword FIFO Data Swapping */
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#define PWMCR_BCTR (1 << 21) /* Byte FIFO Data Swapping */
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#define PWMCR_DBGEN (1 << 22) /* Debug Mode */
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#define PWMCR_WAITEN (1 << 23) /* Wait Mode */
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#define PWMCR_DOZEN (1 << 24) /* Doze Mode */
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#define PWMCR_STOPEN (1 << 25) /* Stop Mode */
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#define PWMCR_FWM(x) (((x) & 0x3) << 26) /* FIFO Water Mark */
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#define MAX_DIV 4096
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#endif
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#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */
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#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */
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#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */
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struct pwm_device {
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struct list_head node;
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struct platform_device *pdev;
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const char *label;
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struct clk *clk;
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int clk_enabled;
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void __iomem *mmio_base;
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unsigned int use_count;
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unsigned int pwm_id;
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};
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int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
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{
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unsigned long long c;
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unsigned long period_cycles, duty_cycles, prescale;
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if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
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return -EINVAL;
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c = clk_get_rate(pwm->clk);
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c = c * period_ns;
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do_div(c, 1000000000);
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period_cycles = c;
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prescale = period_cycles / 0x10000 + 1;
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period_cycles /= prescale;
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c = (unsigned long long)period_cycles * duty_ns;
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do_div(c, period_ns);
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duty_cycles = c;
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#ifdef PWM_VER_2
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writel(duty_cycles, pwm->mmio_base + PWMSAR);
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writel(period_cycles, pwm->mmio_base + PWMPR);
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writel(PWMCR_PRESCALER(prescale - 1) | PWMCR_CLKSRC_IPG_HIGH | PWMCR_EN,
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pwm->mmio_base + PWMCR);
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#elif defined PWM_VER_1
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#error PWM not yet working on MX1 / MX21
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#endif
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return 0;
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}
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EXPORT_SYMBOL(pwm_config);
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int pwm_enable(struct pwm_device *pwm)
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{
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int rc = 0;
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if (!pwm->clk_enabled) {
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rc = clk_enable(pwm->clk);
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if (!rc)
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pwm->clk_enabled = 1;
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}
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return rc;
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}
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EXPORT_SYMBOL(pwm_enable);
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void pwm_disable(struct pwm_device *pwm)
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{
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if (pwm->clk_enabled) {
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clk_disable(pwm->clk);
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pwm->clk_enabled = 0;
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}
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}
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EXPORT_SYMBOL(pwm_disable);
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static DEFINE_MUTEX(pwm_lock);
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static LIST_HEAD(pwm_list);
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struct pwm_device *pwm_request(int pwm_id, const char *label)
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{
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struct pwm_device *pwm;
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int found = 0;
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mutex_lock(&pwm_lock);
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list_for_each_entry(pwm, &pwm_list, node) {
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if (pwm->pwm_id == pwm_id) {
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found = 1;
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break;
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}
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}
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if (found) {
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if (pwm->use_count == 0) {
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pwm->use_count++;
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pwm->label = label;
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} else
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pwm = ERR_PTR(-EBUSY);
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} else
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pwm = ERR_PTR(-ENOENT);
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mutex_unlock(&pwm_lock);
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return pwm;
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}
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EXPORT_SYMBOL(pwm_request);
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void pwm_free(struct pwm_device *pwm)
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{
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mutex_lock(&pwm_lock);
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if (pwm->use_count) {
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pwm->use_count--;
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pwm->label = NULL;
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} else
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pr_warning("PWM device already freed\n");
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mutex_unlock(&pwm_lock);
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}
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EXPORT_SYMBOL(pwm_free);
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static int __devinit mxc_pwm_probe(struct platform_device *pdev)
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{
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struct pwm_device *pwm;
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struct resource *r;
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int ret = 0;
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pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
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if (pwm == NULL) {
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dev_err(&pdev->dev, "failed to allocate memory\n");
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return -ENOMEM;
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}
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pwm->clk = clk_get(&pdev->dev, "pwm");
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if (IS_ERR(pwm->clk)) {
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ret = PTR_ERR(pwm->clk);
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goto err_free;
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}
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pwm->clk_enabled = 0;
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pwm->use_count = 0;
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pwm->pwm_id = pdev->id;
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pwm->pdev = pdev;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (r == NULL) {
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dev_err(&pdev->dev, "no memory resource defined\n");
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ret = -ENODEV;
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goto err_free_clk;
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}
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r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
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if (r == NULL) {
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dev_err(&pdev->dev, "failed to request memory resource\n");
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ret = -EBUSY;
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goto err_free_clk;
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}
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pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
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if (pwm->mmio_base == NULL) {
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dev_err(&pdev->dev, "failed to ioremap() registers\n");
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ret = -ENODEV;
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goto err_free_mem;
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}
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mutex_lock(&pwm_lock);
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list_add_tail(&pwm->node, &pwm_list);
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mutex_unlock(&pwm_lock);
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platform_set_drvdata(pdev, pwm);
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return 0;
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err_free_mem:
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release_mem_region(r->start, r->end - r->start + 1);
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err_free_clk:
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clk_put(pwm->clk);
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err_free:
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kfree(pwm);
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return ret;
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}
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static int __devexit mxc_pwm_remove(struct platform_device *pdev)
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{
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struct pwm_device *pwm;
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struct resource *r;
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pwm = platform_get_drvdata(pdev);
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if (pwm == NULL)
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return -ENODEV;
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mutex_lock(&pwm_lock);
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list_del(&pwm->node);
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mutex_unlock(&pwm_lock);
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iounmap(pwm->mmio_base);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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release_mem_region(r->start, r->end - r->start + 1);
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clk_put(pwm->clk);
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kfree(pwm);
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return 0;
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}
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static struct platform_driver mxc_pwm_driver = {
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.driver = {
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.name = "mxc_pwm",
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},
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.probe = mxc_pwm_probe,
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.remove = __devexit_p(mxc_pwm_remove),
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};
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static int __init mxc_pwm_init(void)
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{
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return platform_driver_register(&mxc_pwm_driver);
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}
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arch_initcall(mxc_pwm_init);
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static void __exit mxc_pwm_exit(void)
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{
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platform_driver_unregister(&mxc_pwm_driver);
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}
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module_exit(mxc_pwm_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
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