can: flexcan: add correctable errors correction when HW supports ECC
commitcdce844865
("can: flexcan: add vf610 support for FlexCAN") From above commit by Stefan Agner, the patch just disables non-correctable errors interrupt and freeze mode. It still can correct the correctable errors since ECC enabled by default after reset (MECR[ECCDIS]=0, enable memory error correct) if HW supports ECC. commit5e269324db
("can: flexcan: disable completely the ECC mechanism") From above commit by Joakim Zhang, the patch disables ECC completely (assert MECR[ECCDIS]) according to the explanation of FLEXCAN_QUIRK_DISABLE_MECR that disable memory error detection. This cause correctable errors cannot be corrected even HW supports ECC. The error correction mechanism ensures that in this 13-bit word, errors in one bit can be corrected (correctable errors) and errors in two bits can be detected but not corrected (non-correctable errors). Errors in more than two bits may not be detected. If HW supports ECC, we can use this to correct the correctable errors detected from FlexCAN memory. Then disable non-correctable errors interrupt and freeze mode to avoid that put FlexCAN in freeze mode. This patch adds correctable errors correction when HW supports ECC, and modify explanation for FLEXCAN_QUIRK_DISABLE_MECR. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20200416093126.15242-1-qiangqing.zhang@nxp.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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@ -190,7 +190,7 @@
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#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
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/* Enable EACEN and RRS bit in ctrl2 */
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#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
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/* Disable Memory error detection */
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/* Disable non-correctable errors interrupt and freeze mode */
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#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
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/* Use timestamp based offloading */
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#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
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@ -1221,28 +1221,43 @@ static int flexcan_chip_start(struct net_device *dev)
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for (i = 0; i < priv->mb_count; i++)
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priv->write(0, ®s->rximr[i]);
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/* On Vybrid, disable memory error detection interrupts
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* and freeze mode.
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* This also works around errata e5295 which generates
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* false positive memory errors and put the device in
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* freeze mode.
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/* On Vybrid, disable non-correctable errors interrupt and
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* freeze mode. It still can correct the correctable errors
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* when HW supports ECC.
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*
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* This also works around errata e5295 which generates false
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* positive memory errors and put the device in freeze mode.
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*/
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if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
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/* Follow the protocol as described in "Detection
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* and Correction of Memory Errors" to write to
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* MECR register
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* MECR register (step 1 - 5)
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*
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* 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
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* 2. set CTRL2[ECRWRE]
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*/
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reg_ctrl2 = priv->read(®s->ctrl2);
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reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
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priv->write(reg_ctrl2, ®s->ctrl2);
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/* 3. clear MECR[ECRWRDIS] */
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reg_mecr = priv->read(®s->mecr);
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reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
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priv->write(reg_mecr, ®s->mecr);
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reg_mecr |= FLEXCAN_MECR_ECCDIS;
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/* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
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reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
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FLEXCAN_MECR_FANCEI_MSK);
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priv->write(reg_mecr, ®s->mecr);
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/* 5. after configuration done, lock MECR by either
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* setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
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*/
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reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
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priv->write(reg_mecr, ®s->mecr);
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reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
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priv->write(reg_ctrl2, ®s->ctrl2);
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}
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err = flexcan_transceiver_enable(priv);
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