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MIPS: Replace use of phys_t with phys_addr_t. 

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2014-11-22 00:22:09 +01:00
parent 34adb28d50
commit 15d45cce3a
23 changed files with 64 additions and 64 deletions
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4
arch/mips/alchemy/common/setup.c
View File

@ -72,7 +72,7 @@ void __init plat_mem_setup(void)
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
/* This routine should be valid for all Au1x based boards */
phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
unsigned long start = ALCHEMY_PCI_MEMWIN_START;
unsigned long end = ALCHEMY_PCI_MEMWIN_END;
@ -83,7 +83,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
/* Check for PCI memory window */
if (phys_addr >= start && (phys_addr + size - 1) <= end)
return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
/* default nop */
return phys_addr;

4
arch/mips/cavium-octeon/dma-octeon.c
View File

@ -262,8 +262,8 @@ char *octeon_swiotlb;
void __init plat_swiotlb_setup(void)
{
int i;
phys_t max_addr;
phys_t addr_size;
phys_addr_t max_addr;
phys_addr_t addr_size;
size_t swiotlbsize;
unsigned long swiotlb_nslabs;

8
arch/mips/include/asm/bootinfo.h
View File

@ -98,16 +98,16 @@ extern unsigned long mips_machtype;
struct boot_mem_map {
int nr_map;
struct boot_mem_map_entry {
phys_t addr; /* start of memory segment */
phys_t size; /* size of memory segment */
phys_addr_t addr; /* start of memory segment */
phys_addr_t size; /* size of memory segment */
long type; /* type of memory segment */
} map[BOOT_MEM_MAP_MAX];
};
extern struct boot_mem_map boot_mem_map;
extern void add_memory_region(phys_t start, phys_t size, long type);
extern void detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max);
extern void add_memory_region(phys_addr_t start, phys_addr_t size, long type);
extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max);
extern void prom_init(void);
extern void prom_free_prom_memory(void);

8
arch/mips/include/asm/io.h
View File

@ -167,7 +167,7 @@ static inline void * isa_bus_to_virt(unsigned long address)
*/
#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
extern void __iounmap(const volatile void __iomem *addr);
#ifndef CONFIG_PCI
@ -175,7 +175,7 @@ struct pci_dev;
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
#endif
static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
void __iomem *addr = plat_ioremap(offset, size, flags);
@ -183,7 +183,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
if (addr)
return addr;
#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
#define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
if (cpu_has_64bit_addresses) {
u64 base = UNCAC_BASE;
@ -197,7 +197,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
return (void __iomem *) (unsigned long) (base + offset);
} else if (__builtin_constant_p(offset) &&
__builtin_constant_p(size) && __builtin_constant_p(flags)) {
phys_t phys_addr, last_addr;
phys_addr_t phys_addr, last_addr;
phys_addr = fixup_bigphys_addr(offset, size);

8
arch/mips/include/asm/mach-au1x00/ioremap.h
View File

@ -12,9 +12,9 @@
#include <linux/types.h>
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
extern phys_addr_t __fixup_bigphys_addr(phys_addr_t, phys_addr_t);
#else
static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
static inline phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
@ -23,12 +23,12 @@ static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
/*
* Allow physical addresses to be fixed up to help 36-bit peripherals.
*/
static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return __fixup_bigphys_addr(phys_addr, size);
}
static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
return NULL;

6
arch/mips/include/asm/mach-bcm63xx/ioremap.h
View File

@ -3,12 +3,12 @@
#include <bcm63xx_cpu.h>
static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline int is_bcm63xx_internal_registers(phys_t offset)
static inline int is_bcm63xx_internal_registers(phys_addr_t offset)
{
switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID:
@ -32,7 +32,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
return 0;
}
static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
if (is_bcm63xx_internal_registers(offset))

4
arch/mips/include/asm/mach-generic/ioremap.h
View File

@ -15,12 +15,12 @@
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
return NULL;

4
arch/mips/include/asm/mach-tx39xx/ioremap.h
View File

@ -15,12 +15,12 @@
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
#define TXX9_DIRECTMAP_BASE 0xff000000ul

4
arch/mips/include/asm/mach-tx49xx/ioremap.h
View File

@ -15,12 +15,12 @@
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
#ifdef CONFIG_64BIT

2
arch/mips/include/asm/mips-cm.h
View File

@ -30,7 +30,7 @@ extern void __iomem *mips_cm_l2sync_base;
* different way by defining a function with the same prototype except for the
* name mips_cm_phys_base (without underscores).
*/
extern phys_t __mips_cm_phys_base(void);
extern phys_addr_t __mips_cm_phys_base(void);
/**
* mips_cm_probe - probe for a Coherence Manager

4
arch/mips/include/asm/mips-cpc.h
View File

@ -25,7 +25,7 @@ extern void __iomem *mips_cpc_base;
* memory mapped registers. This is platform dependant & must therefore be
* implemented per-platform.
*/
extern phys_t mips_cpc_default_phys_base(void);
extern phys_addr_t mips_cpc_default_phys_base(void);
/**
* mips_cpc_phys_base - retrieve the physical base address of the CPC
@ -35,7 +35,7 @@ extern phys_t mips_cpc_default_phys_base(void);
* is present. It may be overriden by individual platforms which determine
* this address in a different way.
*/
extern phys_t __weak mips_cpc_phys_base(void);
extern phys_addr_t __weak mips_cpc_phys_base(void);
/**
* mips_cpc_probe - probe for a Cluster Power Controller

2
arch/mips/include/asm/pci.h
View File

@ -84,7 +84,7 @@ static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
const struct resource *rsrc, resource_size_t *start,
resource_size_t *end)
{
phys_t size = resource_size(rsrc);
phys_addr_t size = resource_size(rsrc);
*start = fixup_bigphys_addr(rsrc->start, size);
*end = rsrc->start + size;

2
arch/mips/include/asm/pgtable.h
View File

@ -428,7 +428,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
unsigned long size,
pgprot_t prot)
{
phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
phys_addr_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
}
#define io_remap_pfn_range io_remap_pfn_range

6
arch/mips/include/asm/types.h
View File

@ -20,12 +20,12 @@
#ifndef __ASSEMBLY__
/*
* Don't use phys_t. You've been warned.
* Don't use phys_addr_t. You've been warned.
*/
#ifdef CONFIG_PHYS_ADDR_T_64BIT
typedef unsigned long long phys_t;
typedef unsigned long long phys_addr_t;
#else
typedef unsigned long phys_t;
typedef unsigned long phys_addr_t;
#endif
#endif /* __ASSEMBLY__ */

2
arch/mips/jz4740/setup.c
View File

@ -32,7 +32,7 @@ static void __init jz4740_detect_mem(void)
{
void __iomem *jz_emc_base;
u32 ctrl, bus, bank, rows, cols;
phys_t size;
phys_addr_t size;
jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100);
ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL);

12
arch/mips/kernel/mips-cm.c
View File

@ -16,7 +16,7 @@
void __iomem *mips_cm_base;
void __iomem *mips_cm_l2sync_base;
phys_t __mips_cm_phys_base(void)
phys_addr_t __mips_cm_phys_base(void)
{
u32 config3 = read_c0_config3();
u32 cmgcr;
@ -30,10 +30,10 @@ phys_t __mips_cm_phys_base(void)
return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
}
phys_t mips_cm_phys_base(void)
phys_addr_t mips_cm_phys_base(void)
__attribute__((weak, alias("__mips_cm_phys_base")));
phys_t __mips_cm_l2sync_phys_base(void)
phys_addr_t __mips_cm_l2sync_phys_base(void)
{
u32 base_reg;
@ -49,13 +49,13 @@ phys_t __mips_cm_l2sync_phys_base(void)
return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
}
phys_t mips_cm_l2sync_phys_base(void)
phys_addr_t mips_cm_l2sync_phys_base(void)
__attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
static void mips_cm_probe_l2sync(void)
{
unsigned major_rev;
phys_t addr;
phys_addr_t addr;
/* L2-only sync was introduced with CM major revision 6 */
major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
@ -78,7 +78,7 @@ static void mips_cm_probe_l2sync(void)
int mips_cm_probe(void)
{
phys_t addr;
phys_addr_t addr;
u32 base_reg;
addr = mips_cm_phys_base();

4
arch/mips/kernel/mips-cpc.c
View File

@ -21,7 +21,7 @@ static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock);
static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
phys_t __weak mips_cpc_phys_base(void)
phys_addr_t __weak mips_cpc_phys_base(void)
{
u32 cpc_base;
@ -44,7 +44,7 @@ phys_t __weak mips_cpc_phys_base(void)
int mips_cpc_probe(void)
{
phys_t addr;
phys_addr_t addr;
unsigned cpu;
for_each_possible_cpu(cpu)

10
arch/mips/kernel/setup.c
View File

@ -82,7 +82,7 @@ static struct resource data_resource = { .name = "Kernel data", };
static void *detect_magic __initdata = detect_memory_region;
void __init add_memory_region(phys_t start, phys_t size, long type)
void __init add_memory_region(phys_addr_t start, phys_addr_t size, long type)
{
int x = boot_mem_map.nr_map;
int i;
@ -127,10 +127,10 @@ void __init add_memory_region(phys_t start, phys_t size, long type)
boot_mem_map.nr_map++;
}
void __init detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max)
void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max)
{
void *dm = &detect_magic;
phys_t size;
phys_addr_t size;
for (size = sz_min; size < sz_max; size <<= 1) {
if (!memcmp(dm, dm + size, sizeof(detect_magic)))
@ -545,9 +545,9 @@ static int __init early_parse_elfcorehdr(char *p)
early_param("elfcorehdr", early_parse_elfcorehdr);
#endif
static void __init arch_mem_addpart(phys_t mem, phys_t end, int type)
static void __init arch_mem_addpart(phys_addr_t mem, phys_addr_t end, int type)
{
phys_t size;
phys_addr_t size;
int i;
size = end - mem;

18
arch/mips/mm/ioremap.c
View File

@ -17,9 +17,9 @@
#include <asm/tlbflush.h>
static inline void remap_area_pte(pte_t * pte, unsigned long address,
phys_t size, phys_t phys_addr, unsigned long flags)
phys_addr_t size, phys_addr_t phys_addr, unsigned long flags)
{
phys_t end;
phys_addr_t end;
unsigned long pfn;
pgprot_t pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | __READABLE
| __WRITEABLE | flags);
@ -43,9 +43,9 @@ static inline void remap_area_pte(pte_t * pte, unsigned long address,
}
static inline int remap_area_pmd(pmd_t * pmd, unsigned long address,
phys_t size, phys_t phys_addr, unsigned long flags)
phys_addr_t size, phys_addr_t phys_addr, unsigned long flags)
{
phys_t end;
phys_addr_t end;
address &= ~PGDIR_MASK;
end = address + size;
@ -64,8 +64,8 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address,
return 0;
}
static int remap_area_pages(unsigned long address, phys_t phys_addr,
phys_t size, unsigned long flags)
static int remap_area_pages(unsigned long address, phys_addr_t phys_addr,
phys_addr_t size, unsigned long flags)
{
int error;
pgd_t * dir;
@ -111,13 +111,13 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr,
* caller shouldn't need to know that small detail.
*/
#define IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
#define IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
void __iomem * __ioremap(phys_addr_t phys_addr, phys_addr_t size, unsigned long flags)
{
struct vm_struct * area;
unsigned long offset;
phys_t last_addr;
phys_addr_t last_addr;
void * addr;
phys_addr = fixup_bigphys_addr(phys_addr, size);

2
arch/mips/mti-malta/malta-init.c
View File

@ -111,7 +111,7 @@ static void __init mips_ejtag_setup(void)
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
}
phys_t mips_cpc_default_phys_base(void)
phys_addr_t mips_cpc_default_phys_base(void)
{
return CPC_BASE_ADDR;
}

8
arch/mips/rb532/prom.c
View File

@ -122,8 +122,8 @@ void __init prom_setup_cmdline(void)
void __init prom_init(void)
{
struct ddr_ram __iomem *ddr;
phys_t memsize;
phys_t ddrbase;
phys_addr_t memsize;
phys_addr_t ddrbase;
ddr = ioremap_nocache(ddr_reg[0].start,
ddr_reg[0].end - ddr_reg[0].start);
@ -133,8 +133,8 @@ void __init prom_init(void)
return;
}
ddrbase = (phys_t)&ddr->ddrbase;
memsize = (phys_t)&ddr->ddrmask;
ddrbase = (phys_addr_t)&ddr->ddrbase;
memsize = (phys_addr_t)&ddr->ddrmask;
memsize = 0 - memsize;
prom_setup_cmdline();

4
arch/mips/sibyte/common/cfe.c
View File

@ -49,8 +49,8 @@
#endif
#define SIBYTE_MAX_MEM_REGIONS 8
phys_t board_mem_region_addrs[SIBYTE_MAX_MEM_REGIONS];
phys_t board_mem_region_sizes[SIBYTE_MAX_MEM_REGIONS];
phys_addr_t board_mem_region_addrs[SIBYTE_MAX_MEM_REGIONS];
phys_addr_t board_mem_region_sizes[SIBYTE_MAX_MEM_REGIONS];
unsigned int board_mem_region_count;
int cfe_cons_handle;

2
arch/mips/sibyte/swarm/platform.c
View File

@ -50,7 +50,7 @@ static struct platform_device swarm_pata_device = {
static int __init swarm_pata_init(void)
{
u8 __iomem *base;
phys_t offset, size;
phys_addr_t offset, size;
struct resource *r;
if (!SIBYTE_HAVE_IDE)