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drm/amd/display: Disable PG on NV12 

[Why]
HW team request to disable PG on NV12 (fixing missed cases)

[How]
Disable dpp and hubp PG

Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alvin Lee 2020-05-12 17:21:54 -04:00 committed by Alex Deucher
parent 891f016d9d
commit 15ce104c5a
1 changed files with 5 additions and 1 deletions
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6
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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@ -4053,8 +4053,12 @@ static bool dcn20_resource_construct(
// to be consumed. We could have created dcn20_init_hw to get
// the same effect by checking ASIC rev, but there was a
// request at some point to not check ASIC rev on hw sequencer.
if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
dc->hwseq->funcs.enable_power_gating_plane = NULL;
dc->debug.disable_dpp_power_gate = true;
dc->debug.disable_hubp_power_gate = true;
}
dc->caps.max_planes = pool->base.pipe_count;