Orion: general cleanup
Various Orion cleanups: - Unify GPL license banner format across all files. - Unify naming of .h double inclusion guard preprocessor macros. - Unify spelling of "PCIe" (variants seen: PCIE, PCIe, PCI-EX.) - Various typo fixes. - Remove __init attributes from prototypes declared in headers. - Remove trailing comments from #endif statements. - Mark a couple of locally-used-only structs static. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
This commit is contained in:
Lennert Buytenhek
Nicolas Pitre
parent
d50c60a87a
commit
159ffb3a04
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@ -5,8 +5,8 @@
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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@ -45,9 +45,9 @@
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DDR 0
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#define TARGET_DEV_BUS 1
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#define TARGET_PCI 3
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#define TARGET_PCIE 4
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#define TARGET_DEV_BUS 1
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#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
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((n) == 1) ? 0xd : \
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((n) == 2) ? 0xb : \
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@ -64,7 +64,7 @@
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#define WIN_EN 1
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/*
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* Helpers to get DDR banks info
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* Helpers to get DDR bank info
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*/
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#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8))
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#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8))
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@ -5,8 +5,8 @@
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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@ -363,7 +363,7 @@ void __init orion_init(void)
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orion_setup_eth_wins();
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/*
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* REgister devices
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* Register devices.
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*/
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platform_device_register(&orion_uart);
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platform_device_register(&orion_ehci0);
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@ -1,13 +1,13 @@
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#ifndef __ARCH_ORION_COMMON_H__
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#define __ARCH_ORION_COMMON_H__
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#ifndef __ARCH_ORION_COMMON_H
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#define __ARCH_ORION_COMMON_H
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/*
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* Basic Orion init functions used early by machine-setup.
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*/
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void __init orion_map_io(void);
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void __init orion_init_irq(void);
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void __init orion_init(void);
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void orion_map_io(void);
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void orion_init_irq(void);
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void orion_init(void);
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extern struct sys_timer orion_timer;
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/*
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@ -43,7 +43,7 @@ struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
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* (/mach-orion/gpio.c).
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*/
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void __init orion_gpio_set_valid_pins(u32 pins);
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void orion_gpio_set_valid_pins(u32 pins);
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void gpio_display(void); /* debug */
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/*
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@ -52,7 +52,7 @@ void gpio_display(void); /* debug */
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struct mv643xx_eth_platform_data;
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void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
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void orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
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/*
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* Orion Sata platform_data, used by machine-setup
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@ -60,7 +60,7 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
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struct mv_sata_platform_data;
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void __init orion_sata_init(struct mv_sata_platform_data *sata_data);
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void orion_sata_init(struct mv_sata_platform_data *sata_data);
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struct machine_desc;
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struct meminfo;
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@ -68,4 +68,5 @@ struct tag;
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extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *,
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char **, struct meminfo *);
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#endif /* __ARCH_ORION_COMMON_H__ */
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#endif
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@ -5,8 +5,8 @@
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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@ -5,8 +5,8 @@
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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@ -6,7 +6,7 @@
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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@ -3,8 +3,8 @@
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*
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* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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@ -1,12 +1,12 @@
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/*
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* arch/arm/mach-orion/pci.c
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*
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* PCI and PCIE functions for Marvell Orion System On Chip
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* PCI and PCIe functions for Marvell Orion System On Chip
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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@ -18,12 +18,12 @@
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#include "common.h"
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/*****************************************************************************
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* Orion has one PCIE controller and one PCI controller.
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* Orion has one PCIe controller and one PCI controller.
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*
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* Note1: The local PCIE bus number is '0'. The local PCI bus number
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* follows the scanned PCIE bridged busses, if any.
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* Note1: The local PCIe bus number is '0'. The local PCI bus number
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* follows the scanned PCIe bridged busses, if any.
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*
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* Note2: It is possible for PCI/PCIE agents to access many subsystem's
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* Note2: It is possible for PCI/PCIe agents to access many subsystem's
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* space, by configuring BARs and Address Decode Windows, e.g. flashes on
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* device bus, Orion registers, etc. However this code only enable the
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* access to DDR banks.
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@ -31,7 +31,7 @@
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/*****************************************************************************
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* PCIE controller
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* PCIe controller
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****************************************************************************/
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#define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE)
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@ -67,7 +67,7 @@ static int pcie_valid_config(int bus, int dev)
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/*
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* PCIE config cycles are done by programming the PCIE_CONF_ADDR register
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* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
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* and then reading the PCIE_CONF_DATA register. Need to make sure these
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* transactions are atomic.
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*/
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@ -133,7 +133,7 @@ static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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return ret;
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}
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struct pci_ops pcie_ops = {
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static struct pci_ops pcie_ops = {
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.read = pcie_rd_conf,
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.write = pcie_wr_conf,
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};
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@ -170,23 +170,23 @@ static int __init pcie_setup(struct pci_sys_data *sys)
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/*
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* IORESOURCE_IO
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*/
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res[0].name = "PCI-EX I/O Space";
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res[0].name = "PCIe I/O Space";
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res[0].flags = IORESOURCE_IO;
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res[0].start = ORION_PCIE_IO_BUS_BASE;
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res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
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if (request_resource(&ioport_resource, &res[0]))
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panic("Request PCIE IO resource failed\n");
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panic("Request PCIe IO resource failed\n");
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sys->resource[0] = &res[0];
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/*
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* IORESOURCE_MEM
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*/
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res[1].name = "PCI-EX Memory Space";
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res[1].name = "PCIe Memory Space";
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res[1].flags = IORESOURCE_MEM;
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res[1].start = ORION_PCIE_MEM_PHYS_BASE;
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res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
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if (request_resource(&iomem_resource, &res[1]))
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panic("Request PCIE Memory resource failed\n");
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panic("Request PCIe Memory resource failed\n");
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sys->resource[1] = &res[1];
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sys->resource[2] = NULL;
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@ -351,7 +351,7 @@ static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
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PCI_FUNC(devfn), where, size, val);
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}
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struct pci_ops pci_ops = {
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static struct pci_ops pci_ops = {
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.read = orion_pci_rd_conf,
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.write = orion_pci_wr_conf,
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};
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@ -508,7 +508,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
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/*****************************************************************************
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* General PCIE + PCI
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* General PCIe + PCI
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****************************************************************************/
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static void __devinit rc_pci_fixup(struct pci_dev *dev)
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{
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*
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* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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@ -1,5 +1,5 @@
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/*
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* linux/include/asm-arm/arch-orion/debug-macro.S
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* include/asm-arm/arch-orion/debug-macro.S
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*
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* Debugging macro include header
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*
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@ -6,8 +6,8 @@
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H__
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#define __ASM_ARCH_HARDWARE_H__
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include "orion.h"
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@ -3,13 +3,13 @@
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*
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* Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#ifndef __ASM_ARCH_IO_H
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#define __ASM_ARCH_IO_H
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#include "orion.h"
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@ -10,8 +10,8 @@
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IRQS_H__
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#define __ASM_ARCH_IRQS_H__
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H
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#include "orion.h" /* need GPIO_MAX */
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@ -58,4 +58,5 @@
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#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
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#endif /* __ASM_ARCH_IRQS_H__ */
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#endif
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* Marvell Orion memory definitions
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*/
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#ifndef __ASM_ARCH_MMU_H
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#define __ASM_ARCH_MMU_H
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#ifndef __ASM_ARCH_MEMORY_H
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#define __ASM_ARCH_MEMORY_H
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#define PHYS_OFFSET UL(0x00000000)
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#define __virt_to_bus(x) __virt_to_phys(x)
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#define __bus_to_virt(x) __phys_to_virt(x)
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#endif
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_ORION_H__
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#define __ASM_ARCH_ORION_H__
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#ifndef __ASM_ARCH_ORION_H
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#define __ASM_ARCH_ORION_H
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/*****************************************************************************
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* Orion Address Maps
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#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
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#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
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#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300)
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#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
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#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
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#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
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#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
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#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300)
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#endif
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@ -3,8 +3,8 @@
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*
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* Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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orion_setbits(CPU_SOFT_RESET, 1);
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}
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#endif
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*
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* Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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@ -3,8 +3,8 @@
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*
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* Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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