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arm64: mm: Rename post_ttbr0_update_workaround 

The post_ttbr0_update_workaround hook applies to any change to TTBRx_EL1.
Since we're using TTBR1 for the ASID, rename the hook to make it clearer
as to what it's doing.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Tested-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon 2017-08-10 13:34:30 +01:00
parent 85d13c0014
commit 158d495899
3 changed files with 4 additions and 5 deletions
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5
arch/arm64/include/asm/assembler.h
View File

@ -477,10 +477,9 @@ alternative_endif
.endm .endm
/* /*
/* * Errata workaround post TTBRx_EL1 update.
* Errata workaround post TTBR0_EL1 update.
*/ */
.macro post_ttbr0_update_workaround .macro post_ttbr_update_workaround
#ifdef CONFIG_CAVIUM_ERRATUM_27456 #ifdef CONFIG_CAVIUM_ERRATUM_27456
alternative_if ARM64_WORKAROUND_CAVIUM_27456 alternative_if ARM64_WORKAROUND_CAVIUM_27456
ic iallu ic iallu

2
arch/arm64/kernel/entry.S
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@ -257,7 +257,7 @@ alternative_else_nop_endif
* Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
* corruption). * corruption).
*/ */
post_ttbr0_update_workaround post_ttbr_update_workaround
.endif .endif
1: 1:
.if \el != 0 .if \el != 0

2
arch/arm64/mm/proc.S
View File

@ -145,7 +145,7 @@ ENTRY(cpu_do_switch_mm)
isb isb
msr ttbr0_el1, x0 // now update TTBR0 msr ttbr0_el1, x0 // now update TTBR0
isb isb
post_ttbr0_update_workaround post_ttbr_update_workaround
ret ret
ENDPROC(cpu_do_switch_mm) ENDPROC(cpu_do_switch_mm)