i2c: designware-pci: Add Haswell PCI IDs
Intel Haswell has the same I2C host controller than Baytrail and it can also be enumerated as a PCI device. Add the PCI IDs to the driver list. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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@ -56,6 +56,7 @@ enum dw_pci_ctl_id_t {
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medfield_5,
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medfield_5,
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baytrail,
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baytrail,
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haswell,
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};
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};
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struct dw_scl_sda_cfg {
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struct dw_scl_sda_cfg {
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@ -95,6 +96,15 @@ static struct dw_scl_sda_cfg byt_config = {
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.sda_hold = 0x6,
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.sda_hold = 0x6,
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};
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};
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/* Haswell HCNT/LCNT/SDA hold time */
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static struct dw_scl_sda_cfg hsw_config = {
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.ss_hcnt = 0x01b0,
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.fs_hcnt = 0x48,
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.ss_lcnt = 0x01fb,
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.fs_lcnt = 0xa0,
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.sda_hold = 0x9,
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};
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static struct dw_pci_controller dw_pci_controllers[] = {
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static struct dw_pci_controller dw_pci_controllers[] = {
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[moorestown_0] = {
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[moorestown_0] = {
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.bus_num = 0,
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.bus_num = 0,
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@ -168,6 +178,15 @@ static struct dw_pci_controller dw_pci_controllers[] = {
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.functionality = I2C_FUNC_10BIT_ADDR,
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.functionality = I2C_FUNC_10BIT_ADDR,
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.scl_sda_cfg = &byt_config,
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.scl_sda_cfg = &byt_config,
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},
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},
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[haswell] = {
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.bus_num = -1,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 100000,
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.functionality = I2C_FUNC_10BIT_ADDR,
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.scl_sda_cfg = &hsw_config,
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},
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};
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};
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static struct i2c_algorithm i2c_dw_algo = {
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static struct i2c_algorithm i2c_dw_algo = {
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.master_xfer = i2c_dw_xfer,
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.master_xfer = i2c_dw_xfer,
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@ -328,6 +347,9 @@ static const struct pci_device_id i2_designware_pci_ids[] = {
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{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
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/* Haswell */
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{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
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{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
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{ 0,}
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{ 0,}
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};
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};
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MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
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MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
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