drm: rcar-du: Add R-Car DSI driver
The driver supports the MIPI DSI/CSI-2 TX encoder found in the R-Car V3U SoC. It currently supports DSI mode only. Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
LUU HOAI
Laurent Pinchart
parent
1a0548ce39
commit
155358310f
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@ -45,6 +45,13 @@ config DRM_RCAR_LVDS
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select OF_FLATTREE
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select OF_OVERLAY
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config DRM_RCAR_MIPI_DSI
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tristate "R-Car DU MIPI DSI Encoder Support"
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depends on DRM && DRM_BRIDGE && OF
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select DRM_MIPI_DSI
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help
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Enable support for the R-Car Display Unit embedded MIPI DSI encoders.
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config DRM_RCAR_VSP
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bool "R-Car DU VSP Compositor Support" if ARM
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default y if ARM64
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@ -19,6 +19,7 @@ obj-$(CONFIG_DRM_RCAR_CMM) += rcar_cmm.o
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obj-$(CONFIG_DRM_RCAR_DU) += rcar-du-drm.o
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obj-$(CONFIG_DRM_RCAR_DW_HDMI) += rcar_dw_hdmi.o
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obj-$(CONFIG_DRM_RCAR_LVDS) += rcar_lvds.o
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obj-$(CONFIG_DRM_RCAR_MIPI_DSI) += rcar_mipi_dsi.o
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# 'remote-endpoint' is fixed up at run-time
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DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint
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@ -0,0 +1,819 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* rcar_mipi_dsi.c -- R-Car MIPI DSI Encoder
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*
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* Copyright (C) 2020 Renesas Electronics Corporation
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_of.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_probe_helper.h>
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#include "rcar_mipi_dsi_regs.h"
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struct rcar_mipi_dsi {
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struct device *dev;
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const struct rcar_mipi_dsi_device_info *info;
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struct reset_control *rstc;
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struct mipi_dsi_host host;
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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struct drm_connector connector;
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void __iomem *mmio;
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struct {
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struct clk *mod;
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struct clk *pll;
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struct clk *dsi;
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} clocks;
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enum mipi_dsi_pixel_format format;
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unsigned int num_data_lanes;
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unsigned int lanes;
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};
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static inline struct rcar_mipi_dsi *
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bridge_to_rcar_mipi_dsi(struct drm_bridge *bridge)
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{
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return container_of(bridge, struct rcar_mipi_dsi, bridge);
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}
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static inline struct rcar_mipi_dsi *
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host_to_rcar_mipi_dsi(struct mipi_dsi_host *host)
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{
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return container_of(host, struct rcar_mipi_dsi, host);
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}
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static const u32 phtw[] = {
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0x01020114, 0x01600115, /* General testing */
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0x01030116, 0x0102011d, /* General testing */
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0x011101a4, 0x018601a4, /* 1Gbps testing */
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0x014201a0, 0x010001a3, /* 1Gbps testing */
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0x0101011f, /* 1Gbps testing */
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};
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static const u32 phtw2[] = {
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0x010c0130, 0x010c0140, /* General testing */
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0x010c0150, 0x010c0180, /* General testing */
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0x010c0190,
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0x010a0160, 0x010a0170,
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0x01800164, 0x01800174, /* 1Gbps testing */
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};
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static const u32 hsfreqrange_table[][2] = {
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{ 80000000U, 0x00 }, { 90000000U, 0x10 }, { 100000000U, 0x20 },
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{ 110000000U, 0x30 }, { 120000000U, 0x01 }, { 130000000U, 0x11 },
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{ 140000000U, 0x21 }, { 150000000U, 0x31 }, { 160000000U, 0x02 },
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{ 170000000U, 0x12 }, { 180000000U, 0x22 }, { 190000000U, 0x32 },
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{ 205000000U, 0x03 }, { 220000000U, 0x13 }, { 235000000U, 0x23 },
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{ 250000000U, 0x33 }, { 275000000U, 0x04 }, { 300000000U, 0x14 },
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{ 325000000U, 0x25 }, { 350000000U, 0x35 }, { 400000000U, 0x05 },
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{ 450000000U, 0x16 }, { 500000000U, 0x26 }, { 550000000U, 0x37 },
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{ 600000000U, 0x07 }, { 650000000U, 0x18 }, { 700000000U, 0x28 },
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{ 750000000U, 0x39 }, { 800000000U, 0x09 }, { 850000000U, 0x19 },
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{ 900000000U, 0x29 }, { 950000000U, 0x3a }, { 1000000000U, 0x0a },
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{ 1050000000U, 0x1a }, { 1100000000U, 0x2a }, { 1150000000U, 0x3b },
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{ 1200000000U, 0x0b }, { 1250000000U, 0x1b }, { 1300000000U, 0x2b },
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{ 1350000000U, 0x3c }, { 1400000000U, 0x0c }, { 1450000000U, 0x1c },
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{ 1500000000U, 0x2c }, { 1550000000U, 0x3d }, { 1600000000U, 0x0d },
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{ 1650000000U, 0x1d }, { 1700000000U, 0x2e }, { 1750000000U, 0x3e },
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{ 1800000000U, 0x0e }, { 1850000000U, 0x1e }, { 1900000000U, 0x2f },
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{ 1950000000U, 0x3f }, { 2000000000U, 0x0f }, { 2050000000U, 0x40 },
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{ 2100000000U, 0x41 }, { 2150000000U, 0x42 }, { 2200000000U, 0x43 },
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{ 2250000000U, 0x44 }, { 2300000000U, 0x45 }, { 2350000000U, 0x46 },
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{ 2400000000U, 0x47 }, { 2450000000U, 0x48 }, { 2500000000U, 0x49 },
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{ /* sentinel */ },
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};
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struct vco_cntrl_value {
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u32 min_freq;
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u32 max_freq;
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u16 value;
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};
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static const struct vco_cntrl_value vco_cntrl_table[] = {
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{ .min_freq = 40000000U, .max_freq = 55000000U, .value = 0x3f },
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{ .min_freq = 52500000U, .max_freq = 80000000U, .value = 0x39 },
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{ .min_freq = 80000000U, .max_freq = 110000000U, .value = 0x2f },
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{ .min_freq = 105000000U, .max_freq = 160000000U, .value = 0x29 },
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{ .min_freq = 160000000U, .max_freq = 220000000U, .value = 0x1f },
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{ .min_freq = 210000000U, .max_freq = 320000000U, .value = 0x19 },
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{ .min_freq = 320000000U, .max_freq = 440000000U, .value = 0x0f },
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{ .min_freq = 420000000U, .max_freq = 660000000U, .value = 0x09 },
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{ .min_freq = 630000000U, .max_freq = 1149000000U, .value = 0x03 },
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{ .min_freq = 1100000000U, .max_freq = 1152000000U, .value = 0x01 },
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{ .min_freq = 1150000000U, .max_freq = 1250000000U, .value = 0x01 },
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{ /* sentinel */ },
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};
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static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data)
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{
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iowrite32(data, dsi->mmio + reg);
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}
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static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg)
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{
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return ioread32(dsi->mmio + reg);
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}
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static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr)
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{
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rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr);
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}
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static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set)
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{
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rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set);
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}
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static int rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi *dsi, u32 phtw)
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{
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u32 status;
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int ret;
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rcar_mipi_dsi_write(dsi, PHTW, phtw);
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ret = read_poll_timeout(rcar_mipi_dsi_read, status,
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!(status & (PHTW_DWEN | PHTW_CWEN)),
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2000, 10000, false, dsi, PHTW);
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if (ret < 0) {
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dev_err(dsi->dev, "PHY test interface write timeout (0x%08x)\n",
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phtw);
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return ret;
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}
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return ret;
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}
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/* -----------------------------------------------------------------------------
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* Hardware Setup
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*/
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struct dsi_setup_info {
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unsigned long fout;
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u16 vco_cntrl;
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u16 prop_cntrl;
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u16 hsfreqrange;
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u16 div;
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unsigned int m;
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unsigned int n;
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};
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static void rcar_mipi_dsi_parameters_calc(struct rcar_mipi_dsi *dsi,
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struct clk *clk, unsigned long target,
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struct dsi_setup_info *setup_info)
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{
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const struct vco_cntrl_value *vco_cntrl;
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unsigned long fout_target;
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unsigned long fin, fout;
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unsigned long hsfreq;
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unsigned int best_err = -1;
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unsigned int divider;
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unsigned int n;
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unsigned int i;
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unsigned int err;
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/*
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* Calculate Fout = dot clock * ColorDepth / (2 * Lane Count)
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* The range out Fout is [40 - 1250] Mhz
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*/
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fout_target = target * mipi_dsi_pixel_format_to_bpp(dsi->format)
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/ (2 * dsi->lanes);
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if (fout_target < 40000000 || fout_target > 1250000000)
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return;
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/* Find vco_cntrl */
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for (vco_cntrl = vco_cntrl_table; vco_cntrl->min_freq != 0; vco_cntrl++) {
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if (fout_target > vco_cntrl->min_freq &&
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fout_target <= vco_cntrl->max_freq) {
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setup_info->vco_cntrl = vco_cntrl->value;
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if (fout_target >= 1150000000)
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setup_info->prop_cntrl = 0x0c;
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else
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setup_info->prop_cntrl = 0x0b;
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break;
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}
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}
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/* Add divider */
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setup_info->div = (setup_info->vco_cntrl & 0x30) >> 4;
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/* Find hsfreqrange */
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hsfreq = fout_target * 2;
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for (i = 0; i < ARRAY_SIZE(hsfreqrange_table); i++) {
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if (hsfreqrange_table[i][0] >= hsfreq) {
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setup_info->hsfreqrange = hsfreqrange_table[i][1];
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break;
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}
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}
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/*
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* Calculate n and m for PLL clock
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* Following the HW manual the ranges of n and m are
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* n = [3-8] and m = [64-625]
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*/
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fin = clk_get_rate(clk);
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divider = 1 << setup_info->div;
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for (n = 3; n < 9; n++) {
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unsigned long fpfd;
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unsigned int m;
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fpfd = fin / n;
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for (m = 64; m < 626; m++) {
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fout = fpfd * m / divider;
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err = abs((long)(fout - fout_target) * 10000 /
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(long)fout_target);
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if (err < best_err) {
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setup_info->m = m - 2;
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setup_info->n = n - 1;
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setup_info->fout = fout;
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best_err = err;
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if (err == 0)
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goto done;
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}
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}
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}
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done:
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dev_dbg(dsi->dev,
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"%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/DIV %u/%u/%u\n",
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clk, fin, setup_info->fout, fout_target, best_err / 100,
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best_err % 100, setup_info->m, setup_info->n, setup_info->div);
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dev_dbg(dsi->dev,
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"vco_cntrl = 0x%x\tprop_cntrl = 0x%x\thsfreqrange = 0x%x\n",
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setup_info->vco_cntrl, setup_info->prop_cntrl,
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setup_info->hsfreqrange);
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}
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static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi,
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const struct drm_display_mode *mode)
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{
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u32 setr;
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u32 vprmset0r;
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u32 vprmset1r;
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u32 vprmset2r;
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u32 vprmset3r;
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u32 vprmset4r;
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/* Configuration for Pixel Stream and Packet Header */
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if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 24)
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rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB24);
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else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 18)
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rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB18);
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else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 16)
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rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB16);
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else {
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dev_warn(dsi->dev, "unsupported format");
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return;
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}
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/* Configuration for Blanking sequence and Input Pixel */
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setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN
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| TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES
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| TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
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rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
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/* Configuration for Video Parameters */
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vprmset0r = (mode->flags & DRM_MODE_FLAG_PVSYNC ?
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TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW)
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| (mode->flags & DRM_MODE_FLAG_PHSYNC ?
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TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW)
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| TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24;
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vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay)
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| TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);
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vprmset2r = TXVMVPRMSET2R_VFP(mode->vsync_start - mode->vdisplay)
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| TXVMVPRMSET2R_VBP(mode->vtotal - mode->vsync_end);
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vprmset3r = TXVMVPRMSET3R_HACTIVE(mode->hdisplay)
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| TXVMVPRMSET3R_HSA(mode->hsync_end - mode->hsync_start);
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vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay)
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| TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end);
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rcar_mipi_dsi_write(dsi, TXVMVPRMSET0R, vprmset0r);
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rcar_mipi_dsi_write(dsi, TXVMVPRMSET1R, vprmset1r);
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rcar_mipi_dsi_write(dsi, TXVMVPRMSET2R, vprmset2r);
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rcar_mipi_dsi_write(dsi, TXVMVPRMSET3R, vprmset3r);
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rcar_mipi_dsi_write(dsi, TXVMVPRMSET4R, vprmset4r);
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}
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static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi,
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const struct drm_display_mode *mode)
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{
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struct dsi_setup_info setup_info = {};
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unsigned int timeout;
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int ret, i;
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int dsi_format;
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u32 phy_setup;
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u32 clockset2, clockset3;
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u32 ppisetr;
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u32 vclkset;
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/* Checking valid format */
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dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
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if (dsi_format < 0) {
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dev_warn(dsi->dev, "invalid format");
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return -EINVAL;
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}
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/* Parameters Calculation */
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rcar_mipi_dsi_parameters_calc(dsi, dsi->clocks.pll,
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mode->clock * 1000, &setup_info);
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/* LPCLK enable */
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rcar_mipi_dsi_set(dsi, LPCLKSET, LPCLKSET_CKEN);
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/* CFGCLK enabled */
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rcar_mipi_dsi_set(dsi, CFGCLKSET, CFGCLKSET_CKEN);
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rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
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rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
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rcar_mipi_dsi_set(dsi, PHTC, PHTC_TESTCLR);
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rcar_mipi_dsi_clr(dsi, PHTC, PHTC_TESTCLR);
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/* PHY setting */
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phy_setup = rcar_mipi_dsi_read(dsi, PHYSETUP);
|
||||
phy_setup &= ~PHYSETUP_HSFREQRANGE_MASK;
|
||||
phy_setup |= PHYSETUP_HSFREQRANGE(setup_info.hsfreqrange);
|
||||
rcar_mipi_dsi_write(dsi, PHYSETUP, phy_setup);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(phtw); i++) {
|
||||
ret = rcar_mipi_dsi_phtw_test(dsi, phtw[i]);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* PLL Clock Setting */
|
||||
rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
|
||||
rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
|
||||
rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
|
||||
|
||||
clockset2 = CLOCKSET2_M(setup_info.m) | CLOCKSET2_N(setup_info.n)
|
||||
| CLOCKSET2_VCO_CNTRL(setup_info.vco_cntrl);
|
||||
clockset3 = CLOCKSET3_PROP_CNTRL(setup_info.prop_cntrl)
|
||||
| CLOCKSET3_INT_CNTRL(0)
|
||||
| CLOCKSET3_CPBIAS_CNTRL(0x10)
|
||||
| CLOCKSET3_GMP_CNTRL(1);
|
||||
rcar_mipi_dsi_write(dsi, CLOCKSET2, clockset2);
|
||||
rcar_mipi_dsi_write(dsi, CLOCKSET3, clockset3);
|
||||
|
||||
rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
|
||||
rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
|
||||
udelay(10);
|
||||
rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
|
||||
|
||||
ppisetr = PPISETR_DLEN_3 | PPISETR_CLEN;
|
||||
rcar_mipi_dsi_write(dsi, PPISETR, ppisetr);
|
||||
|
||||
rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
|
||||
rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_RSTZ);
|
||||
usleep_range(400, 500);
|
||||
|
||||
/* Checking PPI clock status register */
|
||||
for (timeout = 10; timeout > 0; --timeout) {
|
||||
if ((rcar_mipi_dsi_read(dsi, PPICLSR) & PPICLSR_STPST) &&
|
||||
(rcar_mipi_dsi_read(dsi, PPIDLSR) & PPIDLSR_STPST) &&
|
||||
(rcar_mipi_dsi_read(dsi, CLOCKSET1) & CLOCKSET1_LOCK))
|
||||
break;
|
||||
|
||||
usleep_range(1000, 2000);
|
||||
}
|
||||
|
||||
if (!timeout) {
|
||||
dev_err(dsi->dev, "failed to enable PPI clock\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(phtw2); i++) {
|
||||
ret = rcar_mipi_dsi_phtw_test(dsi, phtw2[i]);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Enable DOT clock */
|
||||
vclkset = VCLKSET_CKEN;
|
||||
rcar_mipi_dsi_set(dsi, VCLKSET, vclkset);
|
||||
|
||||
if (dsi_format == 24)
|
||||
vclkset |= VCLKSET_BPP_24;
|
||||
else if (dsi_format == 18)
|
||||
vclkset |= VCLKSET_BPP_18;
|
||||
else if (dsi_format == 16)
|
||||
vclkset |= VCLKSET_BPP_16;
|
||||
else {
|
||||
dev_warn(dsi->dev, "unsupported format");
|
||||
return -EINVAL;
|
||||
}
|
||||
vclkset |= VCLKSET_COLOR_RGB | VCLKSET_DIV(setup_info.div)
|
||||
| VCLKSET_LANE(dsi->lanes - 1);
|
||||
|
||||
rcar_mipi_dsi_set(dsi, VCLKSET, vclkset);
|
||||
|
||||
/* After setting VCLKSET register, enable VCLKEN */
|
||||
rcar_mipi_dsi_set(dsi, VCLKEN, VCLKEN_CKEN);
|
||||
|
||||
dev_dbg(dsi->dev, "DSI device is started\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *dsi)
|
||||
{
|
||||
rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
|
||||
rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
|
||||
|
||||
dev_dbg(dsi->dev, "DSI device is shutdown\n");
|
||||
}
|
||||
|
||||
static int rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi *dsi)
|
||||
{
|
||||
int ret;
|
||||
|
||||
reset_control_deassert(dsi->rstc);
|
||||
|
||||
ret = clk_prepare_enable(dsi->clocks.mod);
|
||||
if (ret < 0)
|
||||
goto err_reset;
|
||||
|
||||
ret = clk_prepare_enable(dsi->clocks.dsi);
|
||||
if (ret < 0)
|
||||
goto err_clock;
|
||||
|
||||
return 0;
|
||||
|
||||
err_clock:
|
||||
clk_disable_unprepare(dsi->clocks.mod);
|
||||
err_reset:
|
||||
reset_control_assert(dsi->rstc);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi *dsi)
|
||||
{
|
||||
clk_disable_unprepare(dsi->clocks.dsi);
|
||||
clk_disable_unprepare(dsi->clocks.mod);
|
||||
|
||||
reset_control_assert(dsi->rstc);
|
||||
}
|
||||
|
||||
static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi)
|
||||
{
|
||||
/*
|
||||
* In HW manual, we need to check TxDDRClkHS-Q Stable? but it dont
|
||||
* write how to check. So we skip this check in this patch
|
||||
*/
|
||||
u32 status;
|
||||
int ret;
|
||||
|
||||
/* Start HS clock. */
|
||||
rcar_mipi_dsi_set(dsi, PPICLCR, PPICLCR_TXREQHS);
|
||||
|
||||
ret = read_poll_timeout(rcar_mipi_dsi_read, status,
|
||||
status & PPICLSR_TOHS,
|
||||
2000, 10000, false, dsi, PPICLSR);
|
||||
if (ret < 0) {
|
||||
dev_err(dsi->dev, "failed to enable HS clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
rcar_mipi_dsi_set(dsi, PPICLSCR, PPICLSCR_TOHS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *dsi)
|
||||
{
|
||||
u32 status;
|
||||
int ret;
|
||||
|
||||
/* Wait for the link to be ready. */
|
||||
ret = read_poll_timeout(rcar_mipi_dsi_read, status,
|
||||
!(status & (LINKSR_LPBUSY | LINKSR_HSBUSY)),
|
||||
2000, 10000, false, dsi, LINKSR);
|
||||
if (ret < 0) {
|
||||
dev_err(dsi->dev, "Link failed to become ready\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* De-assert video FIFO clear. */
|
||||
rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR);
|
||||
|
||||
ret = read_poll_timeout(rcar_mipi_dsi_read, status,
|
||||
status & TXVMSR_VFRDY,
|
||||
2000, 10000, false, dsi, TXVMSR);
|
||||
if (ret < 0) {
|
||||
dev_err(dsi->dev, "Failed to de-assert video FIFO clear\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Enable transmission in video mode. */
|
||||
rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_EN_VIDEO);
|
||||
|
||||
ret = read_poll_timeout(rcar_mipi_dsi_read, status,
|
||||
status & TXVMSR_RDY,
|
||||
2000, 10000, false, dsi, TXVMSR);
|
||||
if (ret < 0) {
|
||||
dev_err(dsi->dev, "Failed to enable video transmission\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Bridge
|
||||
*/
|
||||
|
||||
static int rcar_mipi_dsi_attach(struct drm_bridge *bridge,
|
||||
enum drm_bridge_attach_flags flags)
|
||||
{
|
||||
struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
|
||||
|
||||
return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge,
|
||||
flags);
|
||||
}
|
||||
|
||||
static void rcar_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
|
||||
struct drm_bridge_state *old_bridge_state)
|
||||
{
|
||||
struct drm_atomic_state *state = old_bridge_state->base.state;
|
||||
struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
|
||||
const struct drm_display_mode *mode;
|
||||
struct drm_connector *connector;
|
||||
struct drm_crtc *crtc;
|
||||
int ret;
|
||||
|
||||
connector = drm_atomic_get_new_connector_for_encoder(state,
|
||||
bridge->encoder);
|
||||
crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
|
||||
mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
|
||||
|
||||
ret = rcar_mipi_dsi_clk_enable(dsi);
|
||||
if (ret < 0) {
|
||||
dev_err(dsi->dev, "failed to enable DSI clocks\n");
|
||||
return;
|
||||
}
|
||||
|
||||
ret = rcar_mipi_dsi_startup(dsi, mode);
|
||||
if (ret < 0)
|
||||
goto err_dsi_startup;
|
||||
|
||||
rcar_mipi_dsi_set_display_timing(dsi, mode);
|
||||
|
||||
ret = rcar_mipi_dsi_start_hs_clock(dsi);
|
||||
if (ret < 0)
|
||||
goto err_dsi_start_hs;
|
||||
|
||||
rcar_mipi_dsi_start_video(dsi);
|
||||
|
||||
return;
|
||||
|
||||
err_dsi_start_hs:
|
||||
rcar_mipi_dsi_shutdown(dsi);
|
||||
err_dsi_startup:
|
||||
rcar_mipi_dsi_clk_disable(dsi);
|
||||
}
|
||||
|
||||
static void rcar_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
|
||||
struct drm_bridge_state *old_bridge_state)
|
||||
{
|
||||
struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
|
||||
|
||||
rcar_mipi_dsi_shutdown(dsi);
|
||||
rcar_mipi_dsi_clk_disable(dsi);
|
||||
}
|
||||
|
||||
static enum drm_mode_status
|
||||
rcar_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
|
||||
const struct drm_display_info *info,
|
||||
const struct drm_display_mode *mode)
|
||||
{
|
||||
if (mode->clock > 297000)
|
||||
return MODE_CLOCK_HIGH;
|
||||
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
|
||||
.attach = rcar_mipi_dsi_attach,
|
||||
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
|
||||
.atomic_reset = drm_atomic_helper_bridge_reset,
|
||||
.atomic_enable = rcar_mipi_dsi_atomic_enable,
|
||||
.atomic_disable = rcar_mipi_dsi_atomic_disable,
|
||||
.mode_valid = rcar_mipi_dsi_bridge_mode_valid,
|
||||
};
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Host setting
|
||||
*/
|
||||
|
||||
static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host,
|
||||
struct mipi_dsi_device *device)
|
||||
{
|
||||
struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
|
||||
int ret;
|
||||
|
||||
if (device->lanes > dsi->num_data_lanes)
|
||||
return -EINVAL;
|
||||
|
||||
dsi->lanes = device->lanes;
|
||||
dsi->format = device->format;
|
||||
|
||||
dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
|
||||
1, 0);
|
||||
if (IS_ERR(dsi->next_bridge)) {
|
||||
ret = PTR_ERR(dsi->next_bridge);
|
||||
dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Initialize the DRM bridge. */
|
||||
dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
|
||||
dsi->bridge.of_node = dsi->dev->of_node;
|
||||
drm_bridge_add(&dsi->bridge);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_mipi_dsi_host_detach(struct mipi_dsi_host *host,
|
||||
struct mipi_dsi_device *device)
|
||||
{
|
||||
struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
|
||||
|
||||
drm_bridge_remove(&dsi->bridge);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
|
||||
.attach = rcar_mipi_dsi_host_attach,
|
||||
.detach = rcar_mipi_dsi_host_detach,
|
||||
};
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Probe & Remove
|
||||
*/
|
||||
|
||||
static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
|
||||
{
|
||||
struct device_node *ep;
|
||||
u32 data_lanes[4];
|
||||
int ret;
|
||||
|
||||
ep = of_graph_get_endpoint_by_regs(dsi->dev->of_node, 1, 0);
|
||||
if (!ep) {
|
||||
dev_dbg(dsi->dev, "unconnected port@1\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = of_property_read_variable_u32_array(ep, "data-lanes", data_lanes,
|
||||
1, 4);
|
||||
of_node_put(ep);
|
||||
|
||||
if (ret < 0) {
|
||||
dev_err(dsi->dev, "missing or invalid data-lanes property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
dsi->num_data_lanes = ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *dsi,
|
||||
const char *name,
|
||||
bool optional)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
clk = devm_clk_get(dsi->dev, name);
|
||||
if (!IS_ERR(clk))
|
||||
return clk;
|
||||
|
||||
if (PTR_ERR(clk) == -ENOENT && optional)
|
||||
return NULL;
|
||||
|
||||
dev_err_probe(dsi->dev, PTR_ERR(clk), "failed to get %s clock\n",
|
||||
name ? name : "module");
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *dsi)
|
||||
{
|
||||
dsi->clocks.mod = rcar_mipi_dsi_get_clock(dsi, NULL, false);
|
||||
if (IS_ERR(dsi->clocks.mod))
|
||||
return PTR_ERR(dsi->clocks.mod);
|
||||
|
||||
dsi->clocks.pll = rcar_mipi_dsi_get_clock(dsi, "pll", true);
|
||||
if (IS_ERR(dsi->clocks.pll))
|
||||
return PTR_ERR(dsi->clocks.pll);
|
||||
|
||||
dsi->clocks.dsi = rcar_mipi_dsi_get_clock(dsi, "dsi", true);
|
||||
if (IS_ERR(dsi->clocks.dsi))
|
||||
return PTR_ERR(dsi->clocks.dsi);
|
||||
|
||||
if (!dsi->clocks.pll && !dsi->clocks.dsi) {
|
||||
dev_err(dsi->dev, "no input clock (pll, dsi)\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_mipi_dsi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct rcar_mipi_dsi *dsi;
|
||||
struct resource *mem;
|
||||
int ret;
|
||||
|
||||
dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
|
||||
if (dsi == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, dsi);
|
||||
|
||||
dsi->dev = &pdev->dev;
|
||||
dsi->info = of_device_get_match_data(&pdev->dev);
|
||||
|
||||
ret = rcar_mipi_dsi_parse_dt(dsi);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Acquire resources. */
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
dsi->mmio = devm_ioremap_resource(dsi->dev, mem);
|
||||
if (IS_ERR(dsi->mmio))
|
||||
return PTR_ERR(dsi->mmio);
|
||||
|
||||
ret = rcar_mipi_dsi_get_clocks(dsi);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
dsi->rstc = devm_reset_control_get(dsi->dev, NULL);
|
||||
if (IS_ERR(dsi->rstc)) {
|
||||
dev_err(dsi->dev, "failed to get cpg reset\n");
|
||||
return PTR_ERR(dsi->rstc);
|
||||
}
|
||||
|
||||
/* Initialize the DSI host. */
|
||||
dsi->host.dev = dsi->dev;
|
||||
dsi->host.ops = &rcar_mipi_dsi_host_ops;
|
||||
ret = mipi_dsi_host_register(&dsi->host);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_mipi_dsi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rcar_mipi_dsi *dsi = platform_get_drvdata(pdev);
|
||||
|
||||
mipi_dsi_host_unregister(&dsi->host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rcar_mipi_dsi_of_table[] = {
|
||||
{ .compatible = "renesas,r8a779a0-dsi-csi2-tx" },
|
||||
{ }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, rcar_mipi_dsi_of_table);
|
||||
|
||||
static struct platform_driver rcar_mipi_dsi_platform_driver = {
|
||||
.probe = rcar_mipi_dsi_probe,
|
||||
.remove = rcar_mipi_dsi_remove,
|
||||
.driver = {
|
||||
.name = "rcar-mipi-dsi",
|
||||
.of_match_table = rcar_mipi_dsi_of_table,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(rcar_mipi_dsi_platform_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Renesas R-Car MIPI DSI Encoder Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* rcar_mipi_dsi_regs.h -- R-Car MIPI DSI Interface Registers Definitions
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#ifndef __RCAR_MIPI_DSI_REGS_H__
|
||||
#define __RCAR_MIPI_DSI_REGS_H__
|
||||
|
||||
#define LINKSR 0x010
|
||||
#define LINKSR_LPBUSY (1 << 1)
|
||||
#define LINKSR_HSBUSY (1 << 0)
|
||||
|
||||
/*
|
||||
* Video Mode Register
|
||||
*/
|
||||
#define TXVMSETR 0x180
|
||||
#define TXVMSETR_SYNSEQ_PULSES (0 << 16)
|
||||
#define TXVMSETR_SYNSEQ_EVENTS (1 << 16)
|
||||
#define TXVMSETR_VSTPM (1 << 15)
|
||||
#define TXVMSETR_PIXWDTH (1 << 8)
|
||||
#define TXVMSETR_VSEN_EN (1 << 4)
|
||||
#define TXVMSETR_VSEN_DIS (0 << 4)
|
||||
#define TXVMSETR_HFPBPEN_EN (1 << 2)
|
||||
#define TXVMSETR_HFPBPEN_DIS (0 << 2)
|
||||
#define TXVMSETR_HBPBPEN_EN (1 << 1)
|
||||
#define TXVMSETR_HBPBPEN_DIS (0 << 1)
|
||||
#define TXVMSETR_HSABPEN_EN (1 << 0)
|
||||
#define TXVMSETR_HSABPEN_DIS (0 << 0)
|
||||
|
||||
#define TXVMCR 0x190
|
||||
#define TXVMCR_VFCLR (1 << 12)
|
||||
#define TXVMCR_EN_VIDEO (1 << 0)
|
||||
|
||||
#define TXVMSR 0x1a0
|
||||
#define TXVMSR_STR (1 << 16)
|
||||
#define TXVMSR_VFRDY (1 << 12)
|
||||
#define TXVMSR_ACT (1 << 8)
|
||||
#define TXVMSR_RDY (1 << 0)
|
||||
|
||||
#define TXVMSCR 0x1a4
|
||||
#define TXVMSCR_STR (1 << 16)
|
||||
|
||||
#define TXVMPSPHSETR 0x1c0
|
||||
#define TXVMPSPHSETR_DT_RGB16 (0x0e << 16)
|
||||
#define TXVMPSPHSETR_DT_RGB18 (0x1e << 16)
|
||||
#define TXVMPSPHSETR_DT_RGB18_LS (0x2e << 16)
|
||||
#define TXVMPSPHSETR_DT_RGB24 (0x3e << 16)
|
||||
#define TXVMPSPHSETR_DT_YCBCR16 (0x2c << 16)
|
||||
|
||||
#define TXVMVPRMSET0R 0x1d0
|
||||
#define TXVMVPRMSET0R_HSPOL_HIG (0 << 17)
|
||||
#define TXVMVPRMSET0R_HSPOL_LOW (1 << 17)
|
||||
#define TXVMVPRMSET0R_VSPOL_HIG (0 << 16)
|
||||
#define TXVMVPRMSET0R_VSPOL_LOW (1 << 16)
|
||||
#define TXVMVPRMSET0R_CSPC_RGB (0 << 4)
|
||||
#define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4)
|
||||
#define TXVMVPRMSET0R_BPP_16 (0 << 0)
|
||||
#define TXVMVPRMSET0R_BPP_18 (1 << 0)
|
||||
#define TXVMVPRMSET0R_BPP_24 (2 << 0)
|
||||
|
||||
#define TXVMVPRMSET1R 0x1d4
|
||||
#define TXVMVPRMSET1R_VACTIVE(x) (((x) & 0x7fff) << 16)
|
||||
#define TXVMVPRMSET1R_VSA(x) (((x) & 0xfff) << 0)
|
||||
|
||||
#define TXVMVPRMSET2R 0x1d8
|
||||
#define TXVMVPRMSET2R_VFP(x) (((x) & 0x1fff) << 16)
|
||||
#define TXVMVPRMSET2R_VBP(x) (((x) & 0x1fff) << 0)
|
||||
|
||||
#define TXVMVPRMSET3R 0x1dc
|
||||
#define TXVMVPRMSET3R_HACTIVE(x) (((x) & 0x7fff) << 16)
|
||||
#define TXVMVPRMSET3R_HSA(x) (((x) & 0xfff) << 0)
|
||||
|
||||
#define TXVMVPRMSET4R 0x1e0
|
||||
#define TXVMVPRMSET4R_HFP(x) (((x) & 0x1fff) << 16)
|
||||
#define TXVMVPRMSET4R_HBP(x) (((x) & 0x1fff) << 0)
|
||||
|
||||
/*
|
||||
* PHY-Protocol Interface (PPI) Registers
|
||||
*/
|
||||
#define PPISETR 0x700
|
||||
#define PPISETR_DLEN_0 (0x1 << 0)
|
||||
#define PPISETR_DLEN_1 (0x3 << 0)
|
||||
#define PPISETR_DLEN_2 (0x7 << 0)
|
||||
#define PPISETR_DLEN_3 (0xf << 0)
|
||||
#define PPISETR_CLEN (1 << 8)
|
||||
|
||||
#define PPICLCR 0x710
|
||||
#define PPICLCR_TXREQHS (1 << 8)
|
||||
#define PPICLCR_TXULPSEXT (1 << 1)
|
||||
#define PPICLCR_TXULPSCLK (1 << 0)
|
||||
|
||||
#define PPICLSR 0x720
|
||||
#define PPICLSR_HSTOLP (1 << 27)
|
||||
#define PPICLSR_TOHS (1 << 26)
|
||||
#define PPICLSR_STPST (1 << 0)
|
||||
|
||||
#define PPICLSCR 0x724
|
||||
#define PPICLSCR_HSTOLP (1 << 27)
|
||||
#define PPICLSCR_TOHS (1 << 26)
|
||||
|
||||
#define PPIDLSR 0x760
|
||||
#define PPIDLSR_STPST (0xf << 0)
|
||||
|
||||
/*
|
||||
* Clocks registers
|
||||
*/
|
||||
#define LPCLKSET 0x1000
|
||||
#define LPCLKSET_CKEN (1 << 8)
|
||||
#define LPCLKSET_LPCLKDIV(x) (((x) & 0x3f) << 0)
|
||||
|
||||
#define CFGCLKSET 0x1004
|
||||
#define CFGCLKSET_CKEN (1 << 8)
|
||||
#define CFGCLKSET_CFGCLKDIV(x) (((x) & 0x3f) << 0)
|
||||
|
||||
#define DOTCLKDIV 0x1008
|
||||
#define DOTCLKDIV_CKEN (1 << 8)
|
||||
#define DOTCLKDIV_DOTCLKDIV(x) (((x) & 0x3f) << 0)
|
||||
|
||||
#define VCLKSET 0x100c
|
||||
#define VCLKSET_CKEN (1 << 16)
|
||||
#define VCLKSET_COLOR_RGB (0 << 8)
|
||||
#define VCLKSET_COLOR_YCC (1 << 8)
|
||||
#define VCLKSET_DIV(x) (((x) & 0x3) << 4)
|
||||
#define VCLKSET_BPP_16 (0 << 2)
|
||||
#define VCLKSET_BPP_18 (1 << 2)
|
||||
#define VCLKSET_BPP_18L (2 << 2)
|
||||
#define VCLKSET_BPP_24 (3 << 2)
|
||||
#define VCLKSET_LANE(x) (((x) & 0x3) << 0)
|
||||
|
||||
#define VCLKEN 0x1010
|
||||
#define VCLKEN_CKEN (1 << 0)
|
||||
|
||||
#define PHYSETUP 0x1014
|
||||
#define PHYSETUP_HSFREQRANGE(x) (((x) & 0x7f) << 16)
|
||||
#define PHYSETUP_HSFREQRANGE_MASK (0x7f << 16)
|
||||
#define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8)
|
||||
#define PHYSETUP_SHUTDOWNZ (1 << 1)
|
||||
#define PHYSETUP_RSTZ (1 << 0)
|
||||
|
||||
#define CLOCKSET1 0x101c
|
||||
#define CLOCKSET1_LOCK_PHY (1 << 17)
|
||||
#define CLOCKSET1_LOCK (1 << 16)
|
||||
#define CLOCKSET1_CLKSEL (1 << 8)
|
||||
#define CLOCKSET1_CLKINSEL_EXTAL (0 << 2)
|
||||
#define CLOCKSET1_CLKINSEL_DIG (1 << 2)
|
||||
#define CLOCKSET1_CLKINSEL_DU (1 << 3)
|
||||
#define CLOCKSET1_SHADOW_CLEAR (1 << 1)
|
||||
#define CLOCKSET1_UPDATEPLL (1 << 0)
|
||||
|
||||
#define CLOCKSET2 0x1020
|
||||
#define CLOCKSET2_M(x) (((x) & 0xfff) << 16)
|
||||
#define CLOCKSET2_VCO_CNTRL(x) (((x) & 0x3f) << 8)
|
||||
#define CLOCKSET2_N(x) (((x) & 0xf) << 0)
|
||||
|
||||
#define CLOCKSET3 0x1024
|
||||
#define CLOCKSET3_PROP_CNTRL(x) (((x) & 0x3f) << 24)
|
||||
#define CLOCKSET3_INT_CNTRL(x) (((x) & 0x3f) << 16)
|
||||
#define CLOCKSET3_CPBIAS_CNTRL(x) (((x) & 0x7f) << 8)
|
||||
#define CLOCKSET3_GMP_CNTRL(x) (((x) & 0x3) << 0)
|
||||
|
||||
#define PHTW 0x1034
|
||||
#define PHTW_DWEN (1 << 24)
|
||||
#define PHTW_TESTDIN_DATA(x) (((x) & 0xff) << 16)
|
||||
#define PHTW_CWEN (1 << 8)
|
||||
#define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0)
|
||||
|
||||
#define PHTC 0x103c
|
||||
#define PHTC_TESTCLR (1 << 0)
|
||||
|
||||
#endif /* __RCAR_MIPI_DSI_REGS_H__ */
|
||||
Loading…
Reference in New Issue