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MIPS: BCM63xx: Remove SPI2 register 

This register was introduced with the support of the BCM6368 CPU in the idea
that its internal layout was different from the other CPUs SPI controller.
The controller is actually the same as the one present on BCM6358 so we can
remove this register and use the usual SPI register instead.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: grant.likely@secretlab.ca
Cc: spi-devel-general@lists.sourceforge.net
Patchwork: https://patchwork.linux-mips.org/patch/3316/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Florian Fainelli 2012-07-04 16:58:33 +02:00 committed by Ralf Baechle
parent 7546d71a9c
commit 15514e7838
1 changed files with 1 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@ -102,7 +102,6 @@ enum bcm63xx_regs_set {
RSET_UART1, RSET_UART1,
RSET_GPIO, RSET_GPIO,
RSET_SPI, RSET_SPI,
RSET_SPI2,
RSET_UDC0, RSET_UDC0,
RSET_OHCI0, RSET_OHCI0,
RSET_OHCI_PRIV, RSET_OHCI_PRIV,
@ -166,7 +165,6 @@ enum bcm63xx_regs_set {
#define BCM_6338_UART1_BASE (0xdeadbeef) #define BCM_6338_UART1_BASE (0xdeadbeef)
#define BCM_6338_GPIO_BASE (0xfffe0400) #define BCM_6338_GPIO_BASE (0xfffe0400)
#define BCM_6338_SPI_BASE (0xfffe0c00) #define BCM_6338_SPI_BASE (0xfffe0c00)
#define BCM_6338_SPI2_BASE (0xdeadbeef)
#define BCM_6338_UDC0_BASE (0xdeadbeef) #define BCM_6338_UDC0_BASE (0xdeadbeef)
#define BCM_6338_USBDMA_BASE (0xfffe2400) #define BCM_6338_USBDMA_BASE (0xfffe2400)
#define BCM_6338_OHCI0_BASE (0xdeadbeef) #define BCM_6338_OHCI0_BASE (0xdeadbeef)
@ -210,7 +208,6 @@ enum bcm63xx_regs_set {
#define BCM_6345_UART1_BASE (0xdeadbeef) #define BCM_6345_UART1_BASE (0xdeadbeef)
#define BCM_6345_GPIO_BASE (0xfffe0400) #define BCM_6345_GPIO_BASE (0xfffe0400)
#define BCM_6345_SPI_BASE (0xdeadbeef) #define BCM_6345_SPI_BASE (0xdeadbeef)
#define BCM_6345_SPI2_BASE (0xdeadbeef)
#define BCM_6345_UDC0_BASE (0xdeadbeef) #define BCM_6345_UDC0_BASE (0xdeadbeef)
#define BCM_6345_USBDMA_BASE (0xfffe2800) #define BCM_6345_USBDMA_BASE (0xfffe2800)
#define BCM_6345_ENET0_BASE (0xfffe1800) #define BCM_6345_ENET0_BASE (0xfffe1800)
@ -253,7 +250,6 @@ enum bcm63xx_regs_set {
#define BCM_6348_UART1_BASE (0xdeadbeef) #define BCM_6348_UART1_BASE (0xdeadbeef)
#define BCM_6348_GPIO_BASE (0xfffe0400) #define BCM_6348_GPIO_BASE (0xfffe0400)
#define BCM_6348_SPI_BASE (0xfffe0c00) #define BCM_6348_SPI_BASE (0xfffe0c00)
#define BCM_6348_SPI2_BASE (0xdeadbeef)
#define BCM_6348_UDC0_BASE (0xfffe1000) #define BCM_6348_UDC0_BASE (0xfffe1000)
#define BCM_6348_OHCI0_BASE (0xfffe1b00) #define BCM_6348_OHCI0_BASE (0xfffe1b00)
#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
@ -294,7 +290,6 @@ enum bcm63xx_regs_set {
#define BCM_6358_UART1_BASE (0xfffe0120) #define BCM_6358_UART1_BASE (0xfffe0120)
#define BCM_6358_GPIO_BASE (0xfffe0080) #define BCM_6358_GPIO_BASE (0xfffe0080)
#define BCM_6358_SPI_BASE (0xfffe0800) #define BCM_6358_SPI_BASE (0xfffe0800)
#define BCM_6358_SPI2_BASE (0xfffe0800)
#define BCM_6358_UDC0_BASE (0xfffe0800) #define BCM_6358_UDC0_BASE (0xfffe0800)
#define BCM_6358_OHCI0_BASE (0xfffe1400) #define BCM_6358_OHCI0_BASE (0xfffe1400)
#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
@ -335,8 +330,7 @@ enum bcm63xx_regs_set {
#define BCM_6368_UART0_BASE (0xb0000100) #define BCM_6368_UART0_BASE (0xb0000100)
#define BCM_6368_UART1_BASE (0xb0000120) #define BCM_6368_UART1_BASE (0xb0000120)
#define BCM_6368_GPIO_BASE (0xb0000080) #define BCM_6368_GPIO_BASE (0xb0000080)
#define BCM_6368_SPI_BASE (0xdeadbeef) #define BCM_6368_SPI_BASE (0xb0000800)
#define BCM_6368_SPI2_BASE (0xb0000800)
#define BCM_6368_UDC0_BASE (0xdeadbeef) #define BCM_6368_UDC0_BASE (0xdeadbeef)
#define BCM_6368_OHCI0_BASE (0xb0001600) #define BCM_6368_OHCI0_BASE (0xb0001600)
#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
@ -383,7 +377,6 @@ extern const unsigned long *bcm63xx_regs_base;
__GEN_RSET_BASE(__cpu, UART1) \ __GEN_RSET_BASE(__cpu, UART1) \
__GEN_RSET_BASE(__cpu, GPIO) \ __GEN_RSET_BASE(__cpu, GPIO) \
__GEN_RSET_BASE(__cpu, SPI) \ __GEN_RSET_BASE(__cpu, SPI) \
__GEN_RSET_BASE(__cpu, SPI2) \
__GEN_RSET_BASE(__cpu, UDC0) \ __GEN_RSET_BASE(__cpu, UDC0) \
__GEN_RSET_BASE(__cpu, OHCI0) \ __GEN_RSET_BASE(__cpu, OHCI0) \
__GEN_RSET_BASE(__cpu, OHCI_PRIV) \ __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
@ -422,7 +415,6 @@ extern const unsigned long *bcm63xx_regs_base;
[RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
[RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
[RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
[RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
[RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \