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drm/nouveau/devinit: convert to new-style nvkm_subdev 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:20 +10:00
parent 6625f55c08
commit 151abd44c2
32 changed files with 434 additions and 476 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
View File

@ -1,5 +1,6 @@
#ifndef __NVBIOS_INIT_H__
#define __NVBIOS_INIT_H__
struct nvbios_init {
struct nvkm_subdev *subdev;
struct nvkm_bios *bios;

40
drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h
View File

@ -1,32 +1,30 @@
#ifndef __NVKM_DEVINIT_H__
#define __NVKM_DEVINIT_H__
#include <core/subdev.h>
struct nvkm_devinit;
struct nvkm_devinit {
const struct nvkm_devinit_func *func;
struct nvkm_subdev subdev;
bool post;
void (*meminit)(struct nvkm_devinit *);
int (*pll_set)(struct nvkm_devinit *, u32 type, u32 freq);
u32 (*mmio)(struct nvkm_devinit *, u32 addr);
};
static inline struct nvkm_devinit *
nvkm_devinit(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_DEVINIT);
}
u32 nvkm_devinit_mmio(struct nvkm_devinit *, u32 addr);
int nvkm_devinit_pll_set(struct nvkm_devinit *, u32 type, u32 khz);
void nvkm_devinit_meminit(struct nvkm_devinit *);
u64 nvkm_devinit_disable(struct nvkm_devinit *);
extern struct nvkm_oclass *nv04_devinit_oclass;
extern struct nvkm_oclass *nv05_devinit_oclass;
extern struct nvkm_oclass *nv10_devinit_oclass;
extern struct nvkm_oclass *nv1a_devinit_oclass;
extern struct nvkm_oclass *nv20_devinit_oclass;
extern struct nvkm_oclass *nv50_devinit_oclass;
extern struct nvkm_oclass *g84_devinit_oclass;
extern struct nvkm_oclass *g98_devinit_oclass;
extern struct nvkm_oclass *gt215_devinit_oclass;
extern struct nvkm_oclass *mcp89_devinit_oclass;
extern struct nvkm_oclass *gf100_devinit_oclass;
extern struct nvkm_oclass *gm107_devinit_oclass;
extern struct nvkm_oclass *gm204_devinit_oclass;
int nv04_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int nv05_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int nv10_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int nv1a_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int nv20_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int nv50_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int g84_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int g98_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int gt215_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int mcp89_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int gf100_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int gm107_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
int gm204_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **);
#endif

134
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -79,7 +79,7 @@ nv4_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv04_devinit_new,
.devinit = nv04_devinit_new,
// .fb = nv04_fb_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -99,7 +99,7 @@ nv5_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv05_devinit_new,
.devinit = nv05_devinit_new,
// .fb = nv04_fb_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -119,7 +119,7 @@ nv10_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -138,7 +138,7 @@ nv11_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -159,7 +159,7 @@ nv15_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -180,7 +180,7 @@ nv17_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -201,7 +201,7 @@ nv18_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -222,7 +222,7 @@ nv1a_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -243,7 +243,7 @@ nv1f_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -264,7 +264,7 @@ nv20_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
.devinit = nv20_devinit_new,
// .fb = nv20_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -285,7 +285,7 @@ nv25_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
.devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -306,7 +306,7 @@ nv28_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
.devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -327,7 +327,7 @@ nv2a_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
.devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -348,7 +348,7 @@ nv30_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
.devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -369,7 +369,7 @@ nv31_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
.devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -391,7 +391,7 @@ nv34_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -413,7 +413,7 @@ nv35_chipset = {
.bios = nvkm_bios_new,
.bus = nv04_bus_new,
.clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
.devinit = nv20_devinit_new,
// .fb = nv35_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -434,7 +434,7 @@ nv36_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
.devinit = nv20_devinit_new,
// .fb = nv36_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -456,7 +456,7 @@ nv40_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -481,7 +481,7 @@ nv41_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -506,7 +506,7 @@ nv42_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -531,7 +531,7 @@ nv43_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -556,7 +556,7 @@ nv44_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -581,7 +581,7 @@ nv45_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -606,7 +606,7 @@ nv46_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -631,7 +631,7 @@ nv47_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv47_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -656,7 +656,7 @@ nv49_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -681,7 +681,7 @@ nv4a_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -706,7 +706,7 @@ nv4b_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -731,7 +731,7 @@ nv4c_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -756,7 +756,7 @@ nv4e_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv4e_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv4e_i2c_new,
@ -782,7 +782,7 @@ nv50_chipset = {
.bios = nvkm_bios_new,
.bus = nv50_bus_new,
.clk = nv50_clk_new,
// .devinit = nv50_devinit_new,
.devinit = nv50_devinit_new,
// .fb = nv50_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
@ -809,7 +809,7 @@ nv63_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -834,7 +834,7 @@ nv67_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -859,7 +859,7 @@ nv68_chipset = {
.bios = nvkm_bios_new,
.bus = nv31_bus_new,
.clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
.devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
@ -885,7 +885,7 @@ nv84_chipset = {
.bios = nvkm_bios_new,
.bus = nv50_bus_new,
.clk = g84_clk_new,
// .devinit = g84_devinit_new,
.devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
@ -916,7 +916,7 @@ nv86_chipset = {
.bios = nvkm_bios_new,
.bus = nv50_bus_new,
.clk = g84_clk_new,
// .devinit = g84_devinit_new,
.devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
@ -947,7 +947,7 @@ nv92_chipset = {
.bios = nvkm_bios_new,
.bus = nv50_bus_new,
.clk = g84_clk_new,
// .devinit = g84_devinit_new,
.devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
@ -978,7 +978,7 @@ nv94_chipset = {
.bios = nvkm_bios_new,
.bus = g94_bus_new,
.clk = g84_clk_new,
// .devinit = g84_devinit_new,
.devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
@ -1012,7 +1012,7 @@ nv96_chipset = {
.clk = g84_clk_new,
// .therm = g84_therm_new,
// .mxm = nv50_mxm_new,
// .devinit = g84_devinit_new,
.devinit = g84_devinit_new,
// .mc = g94_mc_new,
.bus = g94_bus_new,
// .timer = nv04_timer_new,
@ -1043,7 +1043,7 @@ nv98_chipset = {
.clk = g84_clk_new,
// .therm = g84_therm_new,
// .mxm = nv50_mxm_new,
// .devinit = g98_devinit_new,
.devinit = g98_devinit_new,
// .mc = g98_mc_new,
.bus = g94_bus_new,
// .timer = nv04_timer_new,
@ -1071,7 +1071,7 @@ nva0_chipset = {
.bios = nvkm_bios_new,
.bus = g94_bus_new,
.clk = g84_clk_new,
// .devinit = g84_devinit_new,
.devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
@ -1102,7 +1102,7 @@ nva3_chipset = {
.bios = nvkm_bios_new,
.bus = g94_bus_new,
.clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
.devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
@ -1135,7 +1135,7 @@ nva5_chipset = {
.bios = nvkm_bios_new,
.bus = g94_bus_new,
.clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
.devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
@ -1167,7 +1167,7 @@ nva8_chipset = {
.bios = nvkm_bios_new,
.bus = g94_bus_new,
.clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
.devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
@ -1199,7 +1199,7 @@ nvaa_chipset = {
.bios = nvkm_bios_new,
.bus = g94_bus_new,
.clk = mcp77_clk_new,
// .devinit = g98_devinit_new,
.devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
@ -1230,7 +1230,7 @@ nvac_chipset = {
.bios = nvkm_bios_new,
.bus = g94_bus_new,
.clk = mcp77_clk_new,
// .devinit = g98_devinit_new,
.devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
@ -1261,7 +1261,7 @@ nvaf_chipset = {
.bios = nvkm_bios_new,
.bus = g94_bus_new,
.clk = gt215_clk_new,
// .devinit = mcp89_devinit_new,
.devinit = mcp89_devinit_new,
// .fb = mcp89_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
@ -1293,7 +1293,7 @@ nvc0_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
@ -1328,7 +1328,7 @@ nvc1_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
@ -1362,7 +1362,7 @@ nvc3_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
@ -1396,7 +1396,7 @@ nvc4_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
@ -1431,7 +1431,7 @@ nvc8_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
@ -1466,7 +1466,7 @@ nvce_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
@ -1501,7 +1501,7 @@ nvcf_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
@ -1535,7 +1535,7 @@ nvd7_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gf110_gpio_new,
@ -1567,7 +1567,7 @@ nvd9_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gf110_gpio_new,
@ -1601,7 +1601,7 @@ nve4_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
@ -1637,7 +1637,7 @@ nve6_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
@ -1673,7 +1673,7 @@ nve7_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
@ -1733,7 +1733,7 @@ nvf0_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
@ -1769,7 +1769,7 @@ nvf1_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
@ -1805,7 +1805,7 @@ nv106_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
@ -1840,7 +1840,7 @@ nv108_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
@ -1875,7 +1875,7 @@ nv117_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.clk = gk104_clk_new,
// .devinit = gm107_devinit_new,
.devinit = gm107_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
// .gpio = gk104_gpio_new,
@ -1904,7 +1904,7 @@ nv124_chipset = {
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
// .devinit = gm204_devinit_new,
.devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
// .gpio = gk104_gpio_new,
@ -1933,7 +1933,7 @@ nv126_chipset = {
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
// .devinit = gm204_devinit_new,
.devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
// .gpio = gk104_gpio_new,

9
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -33,7 +33,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -61,7 +60,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -89,7 +87,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -116,7 +113,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -144,7 +140,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -171,7 +166,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -198,7 +192,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -226,7 +219,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -253,7 +245,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;

7
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -33,7 +33,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@ -62,7 +61,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@ -91,7 +89,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@ -138,7 +135,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@ -167,7 +163,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@ -196,7 +191,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@ -224,7 +218,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;

3
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -33,7 +33,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
@ -72,7 +71,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
@ -108,7 +106,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;

2
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
View File

@ -29,7 +29,6 @@ nv04_identify(struct nvkm_device *device)
switch (device->chipset) {
case 0x04:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
@ -43,7 +42,6 @@ nv04_identify(struct nvkm_device *device)
break;
case 0x05:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
View File

@ -30,7 +30,6 @@ nv10_identify(struct nvkm_device *device)
case 0x10:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
@ -43,7 +42,6 @@ nv10_identify(struct nvkm_device *device)
case 0x15:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
@ -58,7 +56,6 @@ nv10_identify(struct nvkm_device *device)
case 0x16:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
@ -73,7 +70,6 @@ nv10_identify(struct nvkm_device *device)
case 0x1a:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
@ -88,7 +84,6 @@ nv10_identify(struct nvkm_device *device)
case 0x11:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
@ -103,7 +98,6 @@ nv10_identify(struct nvkm_device *device)
case 0x17:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
@ -118,7 +112,6 @@ nv10_identify(struct nvkm_device *device)
case 0x1f:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
@ -133,7 +126,6 @@ nv10_identify(struct nvkm_device *device)
case 0x18:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
View File

@ -30,7 +30,6 @@ nv20_identify(struct nvkm_device *device)
case 0x20:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
@ -45,7 +44,6 @@ nv20_identify(struct nvkm_device *device)
case 0x25:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
@ -60,7 +58,6 @@ nv20_identify(struct nvkm_device *device)
case 0x28:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
@ -75,7 +72,6 @@ nv20_identify(struct nvkm_device *device)
case 0x2a:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;

5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
View File

@ -30,7 +30,6 @@ nv30_identify(struct nvkm_device *device)
case 0x30:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
@ -45,7 +44,6 @@ nv30_identify(struct nvkm_device *device)
case 0x35:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass;
@ -60,7 +58,6 @@ nv30_identify(struct nvkm_device *device)
case 0x31:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
@ -76,7 +73,6 @@ nv30_identify(struct nvkm_device *device)
case 0x36:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass;
@ -92,7 +88,6 @@ nv30_identify(struct nvkm_device *device)
case 0x34:
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View File

@ -31,7 +31,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
@ -50,7 +49,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
@ -69,7 +67,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
@ -88,7 +85,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
@ -107,7 +103,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
@ -126,7 +121,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
@ -145,7 +139,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
@ -164,7 +157,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
@ -183,7 +175,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
@ -202,7 +193,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
@ -221,7 +211,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
@ -240,7 +229,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
@ -259,7 +247,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
@ -278,7 +265,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
@ -297,7 +283,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
@ -316,7 +301,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -33,7 +33,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
@ -54,7 +53,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -78,7 +76,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -102,7 +99,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -126,7 +122,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -150,7 +145,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -174,7 +168,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -198,7 +191,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -222,7 +214,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
@ -246,7 +237,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
@ -270,7 +260,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
@ -296,7 +285,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
@ -321,7 +309,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
@ -346,7 +333,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
View File

@ -236,7 +236,7 @@ gf119_disp_intr_unk2_1(struct nv50_disp *disp, int head)
struct nvkm_devinit *devinit = device->devinit;
u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
if (pclk)
devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head, pclk);
nvkm_wr32(device, 0x612200 + (head * 0x800), 0x00000000);
}

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
View File

@ -358,7 +358,7 @@ nv50_disp_intr_unk20_1(struct nv50_disp *disp, int head)
struct nvkm_devinit *devinit = device->devinit;
u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
if (pclk)
devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head, pclk);
}
static void

12
drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
View File

@ -173,9 +173,7 @@ init_nvreg(struct nvbios_init *init, u32 reg)
if (reg & ~0x00fffffc)
warn("unknown bits in register 0x%08x\n", reg);
if (devinit->mmio)
reg = devinit->mmio(devinit, reg);
return reg;
return nvkm_devinit_mmio(devinit, reg);
}
static u32
@ -338,8 +336,8 @@ static void
init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
{
struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
if (devinit->pll_set && init_exec(init)) {
int ret = devinit->pll_set(devinit, id, freq);
if (init_exec(init)) {
int ret = nvkm_devinit_pll_set(devinit, id, freq);
if (ret)
warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
}
@ -1453,8 +1451,8 @@ init_compute_mem(struct nvbios_init *init)
init->offset += 1;
init_exec_force(init, true);
if (init_exec(init) && devinit->meminit)
devinit->meminit(devinit);
if (init_exec(init))
nvkm_devinit_meminit(devinit);
init_exec_force(init, false);
}

130
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
View File

@ -26,70 +26,104 @@
#include <core/option.h>
#include <subdev/vga.h>
int
_nvkm_devinit_fini(struct nvkm_object *object, bool suspend)
u32
nvkm_devinit_mmio(struct nvkm_devinit *init, u32 addr)
{
struct nvkm_devinit *init = (void *)object;
/* force full reinit on resume */
if (suspend)
init->post = true;
/* unlock the extended vga crtc regs */
nvkm_lockvgac(init->subdev.device, false);
return nvkm_subdev_fini_old(&init->subdev, suspend);
if (init->func->mmio)
addr = init->func->mmio(init, addr);
return addr;
}
int
_nvkm_devinit_init(struct nvkm_object *object)
nvkm_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 khz)
{
struct nvkm_devinit_impl *impl = (void *)object->oclass;
struct nvkm_devinit *init = (void *)object;
int ret;
ret = nvkm_subdev_init_old(&init->subdev);
if (ret)
return ret;
ret = impl->post(&init->subdev, init->post);
if (ret)
return ret;
if (impl->disable)
nv_device(init)->disable_mask |= impl->disable(init);
return 0;
return init->func->pll_set(init, type, khz);
}
void
_nvkm_devinit_dtor(struct nvkm_object *object)
nvkm_devinit_meminit(struct nvkm_devinit *init)
{
struct nvkm_devinit *init = (void *)object;
/* lock crtc regs */
nvkm_lockvgac(init->subdev.device, true);
nvkm_subdev_destroy(&init->subdev);
if (init->func->meminit)
init->func->meminit(init);
}
int
nvkm_devinit_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, int size, void **pobject)
u64
nvkm_devinit_disable(struct nvkm_devinit *init)
{
struct nvkm_devinit_impl *impl = (void *)oclass;
struct nvkm_device *device = nv_device(parent);
struct nvkm_devinit *init;
if (init->func->disable)
return init->func->disable(init);
return 0;
}
static int
nvkm_devinit_fini(struct nvkm_subdev *subdev, bool suspend)
{
struct nvkm_devinit *init = nvkm_devinit(subdev);
/* force full reinit on resume */
if (suspend)
init->post = true;
return 0;
}
static int
nvkm_devinit_preinit(struct nvkm_subdev *subdev)
{
struct nvkm_devinit *init = nvkm_devinit(subdev);
if (init->func->preinit)
init->func->preinit(init);
/* unlock the extended vga crtc regs */
nvkm_lockvgac(subdev->device, false);
return 0;
}
static int
nvkm_devinit_init(struct nvkm_subdev *subdev)
{
struct nvkm_devinit *init = nvkm_devinit(subdev);
int ret;
ret = nvkm_subdev_create_(parent, engine, oclass, 0, "DEVINIT",
"init", size, pobject);
init = *pobject;
ret = init->func->post(init, init->post);
if (ret)
return ret;
init->post = nvkm_boolopt(device->cfgopt, "NvForcePost", false);
init->meminit = impl->meminit;
init->pll_set = impl->pll_set;
init->mmio = impl->mmio;
if (init->func->init)
init->func->init(init);
if (init->func->disable)
subdev->device->disable_mask |= init->func->disable(init);
return 0;
}
static void *
nvkm_devinit_dtor(struct nvkm_subdev *subdev)
{
struct nvkm_devinit *init = nvkm_devinit(subdev);
void *data = init;
if (init->func->dtor)
data = init->func->dtor(init);
/* lock crtc regs */
nvkm_lockvgac(subdev->device, true);
return data;
}
static const struct nvkm_subdev_func
nvkm_devinit = {
.dtor = nvkm_devinit_dtor,
.preinit = nvkm_devinit_preinit,
.init = nvkm_devinit_init,
.fini = nvkm_devinit_fini,
};
void
nvkm_devinit_ctor(const struct nvkm_devinit_func *func,
struct nvkm_device *device, int index,
struct nvkm_devinit *init)
{
nvkm_subdev_ctor(&nvkm_devinit, device, index, 0, &init->subdev);
init->func = func;
init->post = nvkm_boolopt(device->cfgopt, "NvForcePost", false);
}

24
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
View File

@ -51,16 +51,18 @@ g84_devinit_disable(struct nvkm_devinit *init)
return disable;
}
struct nvkm_oclass *
g84_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x84),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nvkm_devinit_fini,
},
static const struct nvkm_devinit_func
g84_devinit = {
.preinit = nv50_devinit_preinit,
.init = nv50_devinit_init,
.post = nv04_devinit_post,
.pll_set = nv50_devinit_pll_set,
.disable = g84_devinit_disable,
.post = nvbios_init,
}.base;
};
int
g84_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv50_devinit_new_(&g84_devinit, device, index, pinit);
}

24
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
View File

@ -50,16 +50,18 @@ g98_devinit_disable(struct nvkm_devinit *init)
return disable;
}
struct nvkm_oclass *
g98_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x98),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nvkm_devinit_fini,
},
static const struct nvkm_devinit_func
g98_devinit = {
.preinit = nv50_devinit_preinit,
.init = nv50_devinit_init,
.post = nv04_devinit_post,
.pll_set = nv50_devinit_pll_set,
.disable = g98_devinit_disable,
.post = nvbios_init,
}.base;
};
int
g98_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv50_devinit_new_(&g98_devinit, device, index, pinit);
}

46
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
View File

@ -90,38 +90,18 @@ gf100_devinit_disable(struct nvkm_devinit *init)
return disable;
}
int
gf100_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_devinit_impl *impl = (void *)oclass;
struct nv50_devinit *init;
u64 disable;
int ret;
ret = nvkm_devinit_create(parent, engine, oclass, &init);
*pobject = nv_object(init);
if (ret)
return ret;
disable = impl->disable(&init->base);
if (disable & (1ULL << NVDEV_ENGINE_DISP))
init->base.post = true;
return 0;
}
struct nvkm_oclass *
gf100_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0xc0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_devinit_ctor,
.dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nvkm_devinit_fini,
},
static const struct nvkm_devinit_func
gf100_devinit = {
.preinit = nv50_devinit_preinit,
.init = nv50_devinit_init,
.post = nv04_devinit_post,
.pll_set = gf100_devinit_pll_set,
.disable = gf100_devinit_disable,
.post = nvbios_init,
}.base;
};
int
gf100_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv50_devinit_new_(&gf100_devinit, device, index, pinit);
}

24
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
View File

@ -44,16 +44,18 @@ gm107_devinit_disable(struct nvkm_devinit *init)
return disable;
}
struct nvkm_oclass *
gm107_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x07),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_devinit_ctor,
.dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nvkm_devinit_fini,
},
static const struct nvkm_devinit_func
gm107_devinit = {
.preinit = nv50_devinit_preinit,
.init = nv50_devinit_init,
.post = nv04_devinit_post,
.pll_set = gf100_devinit_pll_set,
.disable = gm107_devinit_disable,
.post = nvbios_init,
}.base;
};
int
gm107_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv50_devinit_new_(&gm107_devinit, device, index, pinit);
}

29
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
View File

@ -107,9 +107,10 @@ pmu_load(struct nv50_devinit *init, u8 type, bool post,
}
static int
gm204_devinit_post(struct nvkm_subdev *subdev, bool post)
gm204_devinit_post(struct nvkm_devinit *base, bool post)
{
struct nv50_devinit *init = (void *)nvkm_devinit(subdev);
struct nv50_devinit *init = nv50_devinit(base);
struct nvkm_subdev *subdev = &init->base.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios;
struct bit_entry bit_I;
@ -163,16 +164,18 @@ gm204_devinit_post(struct nvkm_subdev *subdev, bool post)
return pmu_load(init, 0x01, post, NULL, NULL);
}
struct nvkm_oclass *
gm204_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x07),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_devinit_ctor,
.dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nvkm_devinit_fini,
},
static const struct nvkm_devinit_func
gm204_devinit = {
.preinit = nv50_devinit_preinit,
.init = nv50_devinit_init,
.post = gm204_devinit_post,
.pll_set = gf100_devinit_pll_set,
.disable = gm107_devinit_disable,
.post = gm204_devinit_post,
}.base;
};
int
gm204_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv50_devinit_new_(&gm204_devinit, device, index, pinit);
}

30
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
View File

@ -99,9 +99,9 @@ gt215_devinit_mmio_part[] = {
};
static u32
gt215_devinit_mmio(struct nvkm_devinit *obj, u32 addr)
gt215_devinit_mmio(struct nvkm_devinit *base, u32 addr)
{
struct nv50_devinit *init = container_of(obj, typeof(*init), base);
struct nv50_devinit *init = nv50_devinit(base);
struct nvkm_device *device = init->base.subdev.device;
u32 *mmio = gt215_devinit_mmio_part;
@ -135,17 +135,19 @@ gt215_devinit_mmio(struct nvkm_devinit *obj, u32 addr)
return addr;
}
struct nvkm_oclass *
gt215_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0xa3),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nvkm_devinit_fini,
},
static const struct nvkm_devinit_func
gt215_devinit = {
.preinit = nv50_devinit_preinit,
.init = nv50_devinit_init,
.post = nv04_devinit_post,
.mmio = gt215_devinit_mmio,
.pll_set = gt215_devinit_pll_set,
.disable = gt215_devinit_disable,
.mmio = gt215_devinit_mmio,
.post = nvbios_init,
}.base;
};
int
gt215_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv50_devinit_new_(&gt215_devinit, device, index, pinit);
}

24
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
View File

@ -51,16 +51,18 @@ mcp89_devinit_disable(struct nvkm_devinit *init)
return disable;
}
struct nvkm_oclass *
mcp89_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0xaf),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nvkm_devinit_fini,
},
static const struct nvkm_devinit_func
mcp89_devinit = {
.preinit = nv50_devinit_preinit,
.init = nv50_devinit_init,
.post = nv04_devinit_post,
.pll_set = gt215_devinit_pll_set,
.disable = mcp89_devinit_disable,
.post = nvbios_init,
}.base;
};
int
mcp89_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv50_devinit_new_(&mcp89_devinit, device, index, pinit);
}

78
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
View File

@ -391,32 +391,25 @@ nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
}
int
nv04_devinit_fini(struct nvkm_object *object, bool suspend)
nv04_devinit_post(struct nvkm_devinit *init, bool execute)
{
struct nv04_devinit *init = (void *)object;
struct nvkm_device *device = init->base.subdev.device;
int ret;
return nvbios_init(&init->subdev, execute);
}
void
nv04_devinit_preinit(struct nvkm_devinit *base)
{
struct nv04_devinit *init = nv04_devinit(base);
struct nvkm_subdev *subdev = &init->base.subdev;
struct nvkm_device *device = subdev->device;
/* make i2c busses accessible */
nvkm_mask(device, 0x000200, 0x00000001, 0x00000001);
ret = nvkm_devinit_fini(&init->base, suspend);
if (ret)
return ret;
/* unslave crtcs */
if (init->owner < 0)
init->owner = nvkm_rdvgaowner(device);
nvkm_wrvgaowner(device, 0);
return 0;
}
int
nv04_devinit_init(struct nvkm_object *object)
{
struct nv04_devinit *init = (void *)object;
struct nvkm_subdev *subdev = &init->base.subdev;
struct nvkm_device *device = subdev->device;
if (!init->base.post) {
u32 htotal = nvkm_rdvgac(device, 0, 0x06);
@ -429,48 +422,45 @@ nv04_devinit_init(struct nvkm_object *object)
init->base.post = true;
}
}
return nvkm_devinit_init(&init->base);
}
void
nv04_devinit_dtor(struct nvkm_object *object)
void *
nv04_devinit_dtor(struct nvkm_devinit *base)
{
struct nv04_devinit *init = (void *)object;
struct nv04_devinit *init = nv04_devinit(base);
/* restore vga owner saved at first init */
nvkm_wrvgaowner(init->base.subdev.device, init->owner);
nvkm_devinit_destroy(&init->base);
return init;
}
int
nv04_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv04_devinit_new_(const struct nvkm_devinit_func *func,
struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
struct nv04_devinit *init;
int ret;
ret = nvkm_devinit_create(parent, engine, oclass, &init);
*pobject = nv_object(init);
if (ret)
return ret;
if (!(init = kzalloc(sizeof(*init), GFP_KERNEL)))
return -ENOMEM;
*pinit = &init->base;
nvkm_devinit_ctor(func, device, index, &init->base);
init->owner = -1;
return 0;
}
struct nvkm_oclass *
nv04_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x04),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
.fini = nv04_devinit_fini,
},
static const struct nvkm_devinit_func
nv04_devinit = {
.dtor = nv04_devinit_dtor,
.preinit = nv04_devinit_preinit,
.post = nv04_devinit_post,
.meminit = nv04_devinit_meminit,
.pll_set = nv04_devinit_pll_set,
.post = nvbios_init,
}.base;
};
int
nv04_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv04_devinit_new_(&nv04_devinit, device, index, pinit);
}

16
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
View File

@ -1,5 +1,6 @@
#ifndef __NVKM_DEVINIT_NV04_H__
#define __NVKM_DEVINIT_NV04_H__
#ifndef __NV04_DEVINIT_H__
#define __NV04_DEVINIT_H__
#define nv04_devinit(p) container_of((p), struct nv04_devinit, base)
#include "priv.h"
struct nvkm_pll_vals;
@ -8,12 +9,11 @@ struct nv04_devinit {
int owner;
};
int nv04_devinit_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
void nv04_devinit_dtor(struct nvkm_object *);
int nv04_devinit_init(struct nvkm_object *);
int nv04_devinit_fini(struct nvkm_object *, bool);
int nv04_devinit_new_(const struct nvkm_devinit_func *, struct nvkm_device *,
int, struct nvkm_devinit **);
void *nv04_devinit_dtor(struct nvkm_devinit *);
void nv04_devinit_preinit(struct nvkm_devinit *);
void nv04_devinit_fini(struct nvkm_devinit *);
int nv04_devinit_pll_set(struct nvkm_devinit *, u32, u32);
void setPLL_single(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);

24
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
View File

@ -126,16 +126,18 @@ out:
fbmem_fini(fb);
}
struct nvkm_oclass *
nv05_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x05),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
.fini = nv04_devinit_fini,
},
static const struct nvkm_devinit_func
nv05_devinit = {
.dtor = nv04_devinit_dtor,
.preinit = nv04_devinit_preinit,
.post = nv04_devinit_post,
.meminit = nv05_devinit_meminit,
.pll_set = nv04_devinit_pll_set,
.post = nvbios_init,
}.base;
};
int
nv05_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv04_devinit_new_(&nv05_devinit, device, index, pinit);
}

24
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
View File

@ -96,16 +96,18 @@ amount_found:
fbmem_fini(fb);
}
struct nvkm_oclass *
nv10_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x10),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
.fini = nv04_devinit_fini,
},
static const struct nvkm_devinit_func
nv10_devinit = {
.dtor = nv04_devinit_dtor,
.preinit = nv04_devinit_preinit,
.post = nv04_devinit_post,
.meminit = nv10_devinit_meminit,
.pll_set = nv04_devinit_pll_set,
.post = nvbios_init,
}.base;
};
int
nv10_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv04_devinit_new_(&nv10_devinit, device, index, pinit);
}

24
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c
View File

@ -26,15 +26,17 @@
#include <subdev/bios.h>
#include <subdev/bios/init.h>
struct nvkm_oclass *
nv1a_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x1a),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
.fini = nv04_devinit_fini,
},
static const struct nvkm_devinit_func
nv1a_devinit = {
.dtor = nv04_devinit_dtor,
.preinit = nv04_devinit_preinit,
.post = nv04_devinit_post,
.pll_set = nv04_devinit_pll_set,
.post = nvbios_init,
}.base;
};
int
nv1a_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv04_devinit_new_(&nv1a_devinit, device, index, pinit);
}

26
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
View File

@ -39,7 +39,7 @@ nv20_devinit_meminit(struct nvkm_devinit *init)
struct io_mapping *fb;
/* Map the framebuffer aperture */
fb = fbmem_init(nv_device(init));
fb = fbmem_init(device);
if (!fb) {
nvkm_error(subdev, "failed to map fb\n");
return;
@ -62,16 +62,18 @@ nv20_devinit_meminit(struct nvkm_devinit *init)
fbmem_fini(fb);
}
struct nvkm_oclass *
nv20_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x20),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
.fini = nv04_devinit_fini,
},
static const struct nvkm_devinit_func
nv20_devinit = {
.dtor = nv04_devinit_dtor,
.preinit = nv04_devinit_preinit,
.post = nv04_devinit_post,
.meminit = nv20_devinit_meminit,
.pll_set = nv04_devinit_pll_set,
.post = nvbios_init,
}.base;
};
int
nv20_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv04_devinit_new_(&nv20_devinit, device, index, pinit);
}

82
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
View File

@ -91,19 +91,27 @@ nv50_devinit_disable(struct nvkm_devinit *init)
return disable;
}
int
nv50_devinit_init(struct nvkm_object *object)
void
nv50_devinit_preinit(struct nvkm_devinit *base)
{
struct nv50_devinit *init = (void *)object;
struct nv50_devinit *init = nv50_devinit(base);
struct nvkm_subdev *subdev = &init->base.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios;
struct nvkm_subdev *ibus = device->ibus;
struct nvbios_outp info;
struct dcb_output outp;
u8 ver = 0xff, hdr, cnt, len;
int ret, i = 0;
/* our heuristics can't detect whether the board has had its
* devinit scripts executed or not if the display engine is
* missing, assume it's a secondary gpu which requires post
*/
if (!init->base.post) {
u64 disable = nvkm_devinit_disable(&init->base);
if (disable & (1ULL << NVDEV_ENGINE_DISP))
init->base.post = true;
}
/* magic to detect whether or not x86 vbios code has executed
* the devinit scripts to initialise the board
*/
if (!init->base.post) {
if (!nvkm_rdvgac(device, 0, 0x00) &&
!nvkm_rdvgac(device, 0, 0x1a)) {
@ -118,10 +126,19 @@ nv50_devinit_init(struct nvkm_object *object)
*/
if (init->base.post && ibus)
nvkm_object_init(&ibus->object);
}
ret = nvkm_devinit_init(&init->base);
if (ret)
return ret;
void
nv50_devinit_init(struct nvkm_devinit *base)
{
struct nv50_devinit *init = nv50_devinit(base);
struct nvkm_subdev *subdev = &init->base.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios;
struct nvbios_outp info;
struct dcb_output outp;
u8 ver = 0xff, hdr, cnt, len;
int i = 0;
/* if we ran the init tables, we have to execute the first script
* pointer of each dcb entry's display encoder table in order
@ -131,7 +148,7 @@ nv50_devinit_init(struct nvkm_object *object)
if (nvbios_outp_match(bios, outp.hasht, outp.hashm,
&ver, &hdr, &cnt, &len, &info)) {
struct nvbios_init exec = {
.subdev = nv_subdev(init),
.subdev = subdev,
.bios = bios,
.offset = info.script[0],
.outp = &outp,
@ -143,36 +160,35 @@ nv50_devinit_init(struct nvkm_object *object)
}
i++;
}
return 0;
}
int
nv50_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv50_devinit_new_(const struct nvkm_devinit_func *func,
struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
struct nv50_devinit *init;
int ret;
ret = nvkm_devinit_create(parent, engine, oclass, &init);
*pobject = nv_object(init);
if (ret)
return ret;
if (!(init = kzalloc(sizeof(*init), GFP_KERNEL)))
return -ENOMEM;
*pinit = &init->base;
nvkm_devinit_ctor(func, device, index, &init->base);
return 0;
}
struct nvkm_oclass *
nv50_devinit_oclass = &(struct nvkm_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x50),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nvkm_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nvkm_devinit_fini,
},
static const struct nvkm_devinit_func
nv50_devinit = {
.preinit = nv50_devinit_preinit,
.init = nv50_devinit_init,
.post = nv04_devinit_post,
.pll_set = nv50_devinit_pll_set,
.disable = nv50_devinit_disable,
.post = nvbios_init,
}.base;
};
int
nv50_devinit_new(struct nvkm_device *device, int index,
struct nvkm_devinit **pinit)
{
return nv50_devinit_new_(&nv50_devinit, device, index, pinit);
}

13
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h
View File

@ -1,5 +1,6 @@
#ifndef __NVKM_DEVINIT_NV50_H__
#define __NVKM_DEVINIT_NV50_H__
#ifndef __NV50_DEVINIT_H__
#define __NV50_DEVINIT_H__
#define nv50_devinit(p) container_of((p), struct nv50_devinit, base)
#include "priv.h"
struct nv50_devinit {
@ -7,10 +8,10 @@ struct nv50_devinit {
u32 r001540;
};
int nv50_devinit_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
int nv50_devinit_init(struct nvkm_object *);
int nv50_devinit_new_(const struct nvkm_devinit_func *, struct nvkm_device *,
int, struct nvkm_devinit **);
void nv50_devinit_preinit(struct nvkm_devinit *);
void nv50_devinit_init(struct nvkm_devinit *);
int nv50_devinit_pll_set(struct nvkm_devinit *, u32, u32);
int gt215_devinit_pll_set(struct nvkm_devinit *, u32, u32);

33
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
View File

@ -1,34 +1,21 @@
#ifndef __NVKM_DEVINIT_PRIV_H__
#define __NVKM_DEVINIT_PRIV_H__
#define nvkm_devinit(p) container_of((p), struct nvkm_devinit, subdev)
#include <subdev/devinit.h>
struct nvkm_devinit_impl {
struct nvkm_oclass base;
struct nvkm_devinit_func {
void *(*dtor)(struct nvkm_devinit *);
void (*preinit)(struct nvkm_devinit *);
void (*init)(struct nvkm_devinit *);
int (*post)(struct nvkm_devinit *, bool post);
u32 (*mmio)(struct nvkm_devinit *, u32);
void (*meminit)(struct nvkm_devinit *);
int (*pll_set)(struct nvkm_devinit *, u32 type, u32 freq);
u64 (*disable)(struct nvkm_devinit *);
u32 (*mmio)(struct nvkm_devinit *, u32);
int (*post)(struct nvkm_subdev *, bool);
};
#define nvkm_devinit_create(p,e,o,d) \
nvkm_devinit_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_devinit_destroy(p) ({ \
struct nvkm_devinit *d = (p); \
_nvkm_devinit_dtor(nv_object(d)); \
})
#define nvkm_devinit_init(p) ({ \
struct nvkm_devinit *d = (p); \
_nvkm_devinit_init(nv_object(d)); \
})
#define nvkm_devinit_fini(p,s) ({ \
struct nvkm_devinit *d = (p); \
_nvkm_devinit_fini(nv_object(d), (s)); \
})
void nvkm_devinit_ctor(const struct nvkm_devinit_func *, struct nvkm_device *,
int index, struct nvkm_devinit *);
int nvkm_devinit_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
void _nvkm_devinit_dtor(struct nvkm_object *);
int _nvkm_devinit_init(struct nvkm_object *);
int _nvkm_devinit_fini(struct nvkm_object *, bool suspend);
int nv04_devinit_post(struct nvkm_devinit *, bool);
#endif