net: atlantic: automatically downgrade the number of queues if necessary
This patch adds support for automatic queue number downgrade. On A2: this is a must have, because only TC0/TC1 support more than 4Q. Other TCs support 4Qs maximum. Thus, on A2 we must downgrade the number of queues per TC to 4, if more than 2 TCs are requested. On A1: this allows using 8TCs even on systems with cpu count >= 8, when we have 8 queues by default. We will just automatically switch to 8TCx4Q mode in this case. Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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7327699f35
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14ef766b13
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@ -793,8 +793,6 @@ static int aq_set_ringparam(struct net_device *ndev,
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dev_close(ndev);
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}
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aq_nic_free_vectors(aq_nic);
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cfg->rxds = max(ring->rx_pending, hw_caps->rxds_min);
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cfg->rxds = min(cfg->rxds, hw_caps->rxds_max);
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cfg->rxds = ALIGN(cfg->rxds, AQ_HW_RXD_MULTIPLE);
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@ -803,15 +801,10 @@ static int aq_set_ringparam(struct net_device *ndev,
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cfg->txds = min(cfg->txds, hw_caps->txds_max);
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cfg->txds = ALIGN(cfg->txds, AQ_HW_TXD_MULTIPLE);
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for (aq_nic->aq_vecs = 0; aq_nic->aq_vecs < cfg->vecs;
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aq_nic->aq_vecs++) {
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aq_nic->aq_vec[aq_nic->aq_vecs] =
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aq_vec_alloc(aq_nic, aq_nic->aq_vecs, cfg);
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if (unlikely(!aq_nic->aq_vec[aq_nic->aq_vecs])) {
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err = -ENOMEM;
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err = aq_nic_realloc_vectors(aq_nic);
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if (err)
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goto err_exit;
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}
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}
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if (ndev_running)
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err = dev_open(ndev, NULL);
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@ -337,9 +337,12 @@ static int aq_validate_mqprio_opt(struct aq_nic_s *self,
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const unsigned int num_tc)
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{
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const bool has_min_rate = !!(mqprio->flags & TC_MQPRIO_F_MIN_RATE);
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struct aq_nic_cfg_s *aq_nic_cfg = aq_nic_get_cfg(self);
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const unsigned int tcs_max = min_t(u8, aq_nic_cfg->aq_hw_caps->tcs_max,
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AQ_CFG_TCS_MAX);
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int i;
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if (num_tc > aq_hw_num_tcs(self->aq_hw)) {
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if (num_tc > tcs_max) {
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netdev_err(self->ndev, "Too many TCs requested\n");
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return -EOPNOTSUPP;
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}
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@ -65,6 +65,33 @@ static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues)
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rss_params->indirection_table[i] = i & (num_rss_queues - 1);
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}
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/* Recalculate the number of vectors */
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static void aq_nic_cfg_update_num_vecs(struct aq_nic_s *self)
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{
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struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
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cfg->vecs = min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF);
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cfg->vecs = min(cfg->vecs, num_online_cpus());
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if (self->irqvecs > AQ_HW_SERVICE_IRQS)
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cfg->vecs = min(cfg->vecs, self->irqvecs - AQ_HW_SERVICE_IRQS);
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/* cfg->vecs should be power of 2 for RSS */
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cfg->vecs = rounddown_pow_of_two(cfg->vecs);
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if (ATL_HW_IS_CHIP_FEATURE(self->aq_hw, ANTIGUA)) {
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if (cfg->tcs > 2)
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cfg->vecs = min(cfg->vecs, 4U);
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}
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if (cfg->vecs <= 4)
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cfg->tc_mode = AQ_TC_MODE_8TCS;
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else
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cfg->tc_mode = AQ_TC_MODE_4TCS;
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/*rss rings */
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cfg->num_rss_queues = min(cfg->vecs, AQ_CFG_NUM_RSS_QUEUES_DEF);
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aq_nic_rss_init(self, cfg->num_rss_queues);
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}
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/* Checks hw_caps and 'corrects' aq_nic_cfg in runtime */
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void aq_nic_cfg_start(struct aq_nic_s *self)
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{
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@ -81,7 +108,6 @@ void aq_nic_cfg_start(struct aq_nic_s *self)
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cfg->rxpageorder = AQ_CFG_RX_PAGEORDER;
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cfg->is_rss = AQ_CFG_IS_RSS_DEF;
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cfg->num_rss_queues = AQ_CFG_NUM_RSS_QUEUES_DEF;
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cfg->aq_rss.base_cpu_number = AQ_CFG_RSS_BASE_CPU_NUM_DEF;
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cfg->fc.req = AQ_CFG_FC_MODE;
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cfg->wol = AQ_CFG_WOL_MODES;
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@ -97,24 +123,7 @@ void aq_nic_cfg_start(struct aq_nic_s *self)
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cfg->rxds = min(cfg->aq_hw_caps->rxds_max, AQ_CFG_RXDS_DEF);
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cfg->txds = min(cfg->aq_hw_caps->txds_max, AQ_CFG_TXDS_DEF);
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/*rss rings */
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cfg->vecs = min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF);
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cfg->vecs = min(cfg->vecs, num_online_cpus());
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if (self->irqvecs > AQ_HW_SERVICE_IRQS)
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cfg->vecs = min(cfg->vecs, self->irqvecs - AQ_HW_SERVICE_IRQS);
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/* cfg->vecs should be power of 2 for RSS */
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if (cfg->vecs >= 8U)
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cfg->vecs = 8U;
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else if (cfg->vecs >= 4U)
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cfg->vecs = 4U;
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else if (cfg->vecs >= 2U)
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cfg->vecs = 2U;
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else
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cfg->vecs = 1U;
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cfg->num_rss_queues = min(cfg->vecs, AQ_CFG_NUM_RSS_QUEUES_DEF);
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aq_nic_rss_init(self, cfg->num_rss_queues);
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aq_nic_cfg_update_num_vecs(self);
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cfg->irq_type = aq_pci_func_get_irq_type(self);
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@ -125,11 +134,6 @@ void aq_nic_cfg_start(struct aq_nic_s *self)
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cfg->vecs = 1U;
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}
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if (cfg->vecs <= 4)
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cfg->tc_mode = AQ_TC_MODE_8TCS;
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else
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cfg->tc_mode = AQ_TC_MODE_4TCS;
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/* Check if we have enough vectors allocated for
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* link status IRQ. If no - we'll know link state from
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* slower service task.
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@ -1219,6 +1223,22 @@ void aq_nic_free_vectors(struct aq_nic_s *self)
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err_exit:;
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}
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int aq_nic_realloc_vectors(struct aq_nic_s *self)
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{
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struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(self);
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aq_nic_free_vectors(self);
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for (self->aq_vecs = 0; self->aq_vecs < cfg->vecs; self->aq_vecs++) {
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self->aq_vec[self->aq_vecs] = aq_vec_alloc(self, self->aq_vecs,
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cfg);
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if (unlikely(!self->aq_vec[self->aq_vecs]))
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return -ENOMEM;
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}
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return 0;
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}
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void aq_nic_shutdown(struct aq_nic_s *self)
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{
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int err = 0;
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@ -1288,6 +1308,7 @@ void aq_nic_release_filter(struct aq_nic_s *self, enum aq_rx_filter_type type,
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int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map)
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{
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struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
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const unsigned int prev_vecs = cfg->vecs;
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bool ndev_running;
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int err = 0;
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int i;
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@ -1319,9 +1340,18 @@ int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map)
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netdev_set_num_tc(self->ndev, cfg->tcs);
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/* Changing the number of TCs might change the number of vectors */
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aq_nic_cfg_update_num_vecs(self);
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if (prev_vecs != cfg->vecs) {
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err = aq_nic_realloc_vectors(self);
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if (err)
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goto err_exit;
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}
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if (ndev_running)
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err = dev_open(self->ndev, NULL);
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err_exit:
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return err;
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}
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@ -177,6 +177,7 @@ void aq_nic_deinit(struct aq_nic_s *self, bool link_down);
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void aq_nic_set_power(struct aq_nic_s *self);
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void aq_nic_free_hot_resources(struct aq_nic_s *self);
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void aq_nic_free_vectors(struct aq_nic_s *self);
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int aq_nic_realloc_vectors(struct aq_nic_s *self);
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int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu);
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int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev);
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int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags);
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