drm/i915/i915_drv.h: switch to kernel types
Mixed C99 and kernel types use is getting ugly. Prefer kernel types. sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g' Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190118120125.15484-7-jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
ba3f4d0ad3
commit
143c335ad2
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@ -334,16 +334,16 @@ struct drm_i915_display_funcs {
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struct intel_csr {
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struct work_struct work;
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const char *fw_path;
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uint32_t required_version;
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uint32_t max_fw_size; /* bytes */
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uint32_t *dmc_payload;
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uint32_t dmc_fw_size; /* dwords */
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uint32_t version;
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uint32_t mmio_count;
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u32 required_version;
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u32 max_fw_size; /* bytes */
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u32 *dmc_payload;
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u32 dmc_fw_size; /* dwords */
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u32 version;
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u32 mmio_count;
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i915_reg_t mmioaddr[8];
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uint32_t mmiodata[8];
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uint32_t dc_state;
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uint32_t allowed_dc_mask;
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u32 mmiodata[8];
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u32 dc_state;
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u32 allowed_dc_mask;
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intel_wakeref_t wakeref;
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};
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@ -400,7 +400,7 @@ struct intel_fbc {
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struct {
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unsigned int mode_flags;
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uint32_t hsw_bdw_pixel_rate;
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u32 hsw_bdw_pixel_rate;
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} crtc;
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struct {
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@ -419,7 +419,7 @@ struct intel_fbc {
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int y;
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uint16_t pixel_blend_mode;
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u16 pixel_blend_mode;
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} plane;
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struct {
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@ -559,7 +559,7 @@ struct i915_suspend_saved_registers {
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u32 saveSWF0[16];
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u32 saveSWF1[16];
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u32 saveSWF3[3];
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uint64_t saveFENCE[I915_MAX_NUM_FENCES];
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u64 saveFENCE[I915_MAX_NUM_FENCES];
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u32 savePCH_PORT_HOTPLUG;
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u16 saveGCDGMBUS;
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};
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@ -906,9 +906,9 @@ struct i915_gem_mm {
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atomic_t bsd_engine_dispatch_index;
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/** Bit 6 swizzling required for X tiling */
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uint32_t bit_6_swizzle_x;
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u32 bit_6_swizzle_x;
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/** Bit 6 swizzling required for Y tiling */
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uint32_t bit_6_swizzle_y;
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u32 bit_6_swizzle_y;
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/* accounting, useful for userland debugging */
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spinlock_t object_stat_lock;
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@ -935,20 +935,20 @@ struct ddi_vbt_port_info {
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* populate this field.
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*/
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#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
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uint8_t hdmi_level_shift;
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u8 hdmi_level_shift;
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uint8_t supports_dvi:1;
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uint8_t supports_hdmi:1;
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uint8_t supports_dp:1;
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uint8_t supports_edp:1;
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uint8_t supports_typec_usb:1;
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uint8_t supports_tbt:1;
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u8 supports_dvi:1;
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u8 supports_hdmi:1;
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u8 supports_dp:1;
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u8 supports_edp:1;
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u8 supports_typec_usb:1;
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u8 supports_tbt:1;
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uint8_t alternate_aux_channel;
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uint8_t alternate_ddc_pin;
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u8 alternate_aux_channel;
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u8 alternate_ddc_pin;
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uint8_t dp_boost_level;
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uint8_t hdmi_boost_level;
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u8 dp_boost_level;
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u8 hdmi_boost_level;
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int dp_max_link_rate; /* 0 for not limited by VBT */
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};
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@ -1039,41 +1039,41 @@ enum intel_ddb_partitioning {
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struct intel_wm_level {
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bool enable;
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uint32_t pri_val;
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uint32_t spr_val;
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uint32_t cur_val;
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uint32_t fbc_val;
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u32 pri_val;
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u32 spr_val;
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u32 cur_val;
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u32 fbc_val;
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};
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struct ilk_wm_values {
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uint32_t wm_pipe[3];
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uint32_t wm_lp[3];
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uint32_t wm_lp_spr[3];
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uint32_t wm_linetime[3];
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u32 wm_pipe[3];
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u32 wm_lp[3];
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u32 wm_lp_spr[3];
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u32 wm_linetime[3];
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bool enable_fbc_wm;
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enum intel_ddb_partitioning partitioning;
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};
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struct g4x_pipe_wm {
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uint16_t plane[I915_MAX_PLANES];
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uint16_t fbc;
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u16 plane[I915_MAX_PLANES];
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u16 fbc;
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};
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struct g4x_sr_wm {
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uint16_t plane;
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uint16_t cursor;
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uint16_t fbc;
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u16 plane;
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u16 cursor;
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u16 fbc;
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};
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struct vlv_wm_ddl_values {
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uint8_t plane[I915_MAX_PLANES];
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u8 plane[I915_MAX_PLANES];
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};
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struct vlv_wm_values {
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struct g4x_pipe_wm pipe[3];
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struct g4x_sr_wm sr;
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struct vlv_wm_ddl_values ddl[3];
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uint8_t level;
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u8 level;
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bool cxsr;
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};
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@ -1087,10 +1087,10 @@ struct g4x_wm_values {
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};
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struct skl_ddb_entry {
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uint16_t start, end; /* in number of blocks, 'end' is exclusive */
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u16 start, end; /* in number of blocks, 'end' is exclusive */
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};
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static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
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static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
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{
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return entry->end - entry->start;
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}
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@ -1114,8 +1114,8 @@ struct skl_ddb_values {
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};
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struct skl_wm_level {
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uint16_t plane_res_b;
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uint8_t plane_res_l;
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u16 plane_res_b;
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u8 plane_res_l;
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bool plane_en;
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};
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@ -1124,15 +1124,15 @@ struct skl_wm_params {
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bool x_tiled, y_tiled;
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bool rc_surface;
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bool is_planar;
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uint32_t width;
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uint8_t cpp;
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uint32_t plane_pixel_rate;
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uint32_t y_min_scanlines;
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uint32_t plane_bytes_per_line;
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u32 width;
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u8 cpp;
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u32 plane_pixel_rate;
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u32 y_min_scanlines;
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u32 plane_bytes_per_line;
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uint_fixed_16_16_t plane_blocks_per_line;
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uint_fixed_16_16_t y_tile_minimum;
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uint32_t linetime_us;
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uint32_t dbuf_block_size;
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u32 linetime_us;
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u32 dbuf_block_size;
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};
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/*
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@ -1515,14 +1515,14 @@ struct drm_i915_private {
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* Base address of where the gmbus and gpio blocks are located (either
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* on PCH or on SoC for platforms without PCH).
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*/
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uint32_t gpio_mmio_base;
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u32 gpio_mmio_base;
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/* MMIO base address for MIPI regs */
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uint32_t mipi_mmio_base;
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u32 mipi_mmio_base;
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uint32_t psr_mmio_base;
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u32 psr_mmio_base;
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uint32_t pps_mmio_base;
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u32 pps_mmio_base;
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wait_queue_head_t gmbus_wait_queue;
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@ -1777,17 +1777,17 @@ struct drm_i915_private {
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* in 0.5us units for WM1+.
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*/
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/* primary */
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uint16_t pri_latency[5];
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u16 pri_latency[5];
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/* sprite */
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uint16_t spr_latency[5];
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u16 spr_latency[5];
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/* cursor */
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uint16_t cur_latency[5];
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u16 cur_latency[5];
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/*
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* Raw watermark memory latency values
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* for SKL for all 8 levels
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* in 1us units.
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*/
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uint16_t skl_latency[8];
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u16 skl_latency[8];
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/* current hardware state */
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union {
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@ -1797,7 +1797,7 @@ struct drm_i915_private {
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struct g4x_wm_values g4x;
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};
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uint8_t max_level;
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u8 max_level;
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/*
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* Should be held around atomic WM register writing; also
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@ -2686,45 +2686,45 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
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void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
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void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
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void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
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uint32_t mask,
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uint32_t bits);
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u32 mask,
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u32 bits);
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void ilk_update_display_irq(struct drm_i915_private *dev_priv,
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uint32_t interrupt_mask,
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uint32_t enabled_irq_mask);
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u32 interrupt_mask,
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u32 enabled_irq_mask);
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static inline void
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ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
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ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
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{
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ilk_update_display_irq(dev_priv, bits, bits);
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}
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static inline void
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ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
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ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
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{
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ilk_update_display_irq(dev_priv, bits, 0);
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}
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void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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uint32_t interrupt_mask,
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uint32_t enabled_irq_mask);
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u32 interrupt_mask,
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u32 enabled_irq_mask);
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static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
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enum pipe pipe, uint32_t bits)
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enum pipe pipe, u32 bits)
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{
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bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
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}
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static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
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enum pipe pipe, uint32_t bits)
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enum pipe pipe, u32 bits)
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{
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bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
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}
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
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uint32_t interrupt_mask,
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uint32_t enabled_irq_mask);
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u32 interrupt_mask,
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u32 enabled_irq_mask);
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static inline void
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ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
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ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
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{
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ibx_display_interrupt_update(dev_priv, bits, bits);
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}
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static inline void
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ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
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ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
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{
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ibx_display_interrupt_update(dev_priv, bits, 0);
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}
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@ -2984,7 +2984,7 @@ int i915_gem_dumb_create(struct drm_file *file_priv,
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struct drm_device *dev,
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struct drm_mode_create_dumb *args);
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int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
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uint32_t handle, uint64_t *offset);
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u32 handle, u64 *offset);
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int i915_gem_mmap_gtt_version(void);
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void i915_gem_track_fb(struct drm_i915_gem_object *old,
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@ -3125,7 +3125,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file);
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void i915_oa_init_reg_state(struct intel_engine_cs *engine,
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struct i915_gem_context *ctx,
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uint32_t *reg_state);
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u32 *reg_state);
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/* i915_gem_evict.c */
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int __must_check i915_gem_evict_something(struct i915_address_space *vm,
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@ -3377,10 +3377,10 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
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enum dpio_phy phy);
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bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
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enum dpio_phy phy);
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uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
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u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
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void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
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uint8_t lane_lat_optim_mask);
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uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
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u8 lane_lat_optim_mask);
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u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
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void chv_set_phy_signal_level(struct intel_encoder *encoder,
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u32 deemph_reg_value, u32 margin_reg_value,
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