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MIPS: Loongson: Modify ChipConfig register definition 

This patch is prepared for Multi-chip interconnection. Since each chip
has a ChipConfig register, LOONGSON_CHIPCFG should be an array.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7185/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Huacai Chen 2014-06-26 11:41:27 +08:00 committed by Ralf Baechle
parent bda4584cd9
commit 140e39c1e3
7 changed files with 28 additions and 14 deletions
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7
arch/mips/include/asm/mach-loongson/loongson.h
View File

@ -249,8 +249,11 @@ static inline void do_perfcnt_IRQ(void)
#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) #define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) #define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
/* Chip Config */ #define MAX_PACKAGES 4
#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
extern u64 loongson_chipcfg[MAX_PACKAGES];
#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
/* pcimap */ /* pcimap */

11
arch/mips/loongson/common/env.c
View File

@ -27,6 +27,8 @@ EXPORT_SYMBOL(cpu_clock_freq);
struct efi_memory_map_loongson *loongson_memmap; struct efi_memory_map_loongson *loongson_memmap;
struct loongson_system_configuration loongson_sysconf; struct loongson_system_configuration loongson_sysconf;
u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
#define parse_even_earlier(res, option, p) \ #define parse_even_earlier(res, option, p) \
do { \ do { \
unsigned int tmp __maybe_unused; \ unsigned int tmp __maybe_unused; \
@ -77,6 +79,15 @@ void __init prom_init_env(void)
cpu_clock_freq = ecpu->cpu_clock_freq; cpu_clock_freq = ecpu->cpu_clock_freq;
loongson_sysconf.cputype = ecpu->cputype; loongson_sysconf.cputype = ecpu->cputype;
if (ecpu->cputype == Loongson_3A) {
loongson_chipcfg[0] = 0x900000001fe00180;
loongson_chipcfg[1] = 0x900010001fe00180;
loongson_chipcfg[2] = 0x900020001fe00180;
loongson_chipcfg[3] = 0x900030001fe00180;
} else {
loongson_chipcfg[0] = 0x900000001fe00180;
}
loongson_sysconf.nr_cpus = ecpu->nr_cpus; loongson_sysconf.nr_cpus = ecpu->nr_cpus;
if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0) if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0)
loongson_sysconf.nr_cpus = NR_CPUS; loongson_sysconf.nr_cpus = NR_CPUS;

8
arch/mips/loongson/common/pm.c
View File

@ -79,7 +79,7 @@ int __weak wakeup_loongson(void)
static void wait_for_wakeup_events(void) static void wait_for_wakeup_events(void)
{ {
while (!wakeup_loongson()) while (!wakeup_loongson())
LOONGSON_CHIPCFG0 &= ~0x7; LOONGSON_CHIPCFG(0) &= ~0x7;
} }
/* /*
@ -102,15 +102,15 @@ static void loongson_suspend_enter(void)
stop_perf_counters(); stop_perf_counters();
cached_cpu_freq = LOONGSON_CHIPCFG0; cached_cpu_freq = LOONGSON_CHIPCFG(0);
/* Put CPU into wait mode */ /* Put CPU into wait mode */
LOONGSON_CHIPCFG0 &= ~0x7; LOONGSON_CHIPCFG(0) &= ~0x7;
/* wait for the given events to wakeup cpu from wait mode */ /* wait for the given events to wakeup cpu from wait mode */
wait_for_wakeup_events(); wait_for_wakeup_events();
LOONGSON_CHIPCFG0 = cached_cpu_freq; LOONGSON_CHIPCFG(0) = cached_cpu_freq;
mmiowb(); mmiowb();
} }

4
arch/mips/loongson/lemote-2f/clock.c
View File

@ -114,9 +114,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
clk->rate = rate; clk->rate = rate;
regval = LOONGSON_CHIPCFG0; regval = LOONGSON_CHIPCFG(0);
regval = (regval & ~0x7) | (pos->driver_data - 1); regval = (regval & ~0x7) | (pos->driver_data - 1);
LOONGSON_CHIPCFG0 = regval; LOONGSON_CHIPCFG(0) = regval;
return ret; return ret;
} }

2
arch/mips/loongson/lemote-2f/reset.c
View File

@ -28,7 +28,7 @@ static void reset_cpu(void)
* reset cpu to full speed, this is needed when enabling cpu frequency * reset cpu to full speed, this is needed when enabling cpu frequency
* scalling * scalling
*/ */
LOONGSON_CHIPCFG0 |= 0x7; LOONGSON_CHIPCFG(0) |= 0x7;
} }
/* reset support for fuloong2f */ /* reset support for fuloong2f */

4
arch/mips/loongson/loongson-3/smp.c
View File

@ -399,12 +399,12 @@ static int loongson3_cpu_callback(struct notifier_block *nfb,
case CPU_POST_DEAD: case CPU_POST_DEAD:
case CPU_POST_DEAD_FROZEN: case CPU_POST_DEAD_FROZEN:
pr_info("Disable clock for CPU#%d\n", cpu); pr_info("Disable clock for CPU#%d\n", cpu);
LOONGSON_CHIPCFG0 &= ~(1 << (12 + cpu)); LOONGSON_CHIPCFG(0) &= ~(1 << (12 + cpu));
break; break;
case CPU_UP_PREPARE: case CPU_UP_PREPARE:
case CPU_UP_PREPARE_FROZEN: case CPU_UP_PREPARE_FROZEN:
pr_info("Enable clock for CPU#%d\n", cpu); pr_info("Enable clock for CPU#%d\n", cpu);
LOONGSON_CHIPCFG0 |= 1 << (12 + cpu); LOONGSON_CHIPCFG(0) |= 1 << (12 + cpu);
break; break;
} }

6
drivers/cpufreq/loongson2_cpufreq.c
View File

@ -148,9 +148,9 @@ static void loongson2_cpu_wait(void)
u32 cpu_freq; u32 cpu_freq;
spin_lock_irqsave(&loongson2_wait_lock, flags); spin_lock_irqsave(&loongson2_wait_lock, flags);
cpu_freq = LOONGSON_CHIPCFG0; cpu_freq = LOONGSON_CHIPCFG(0);
LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */ LOONGSON_CHIPCFG(0) &= ~0x7; /* Put CPU into wait mode */
LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */ LOONGSON_CHIPCFG(0) = cpu_freq; /* Restore CPU state */
spin_unlock_irqrestore(&loongson2_wait_lock, flags); spin_unlock_irqrestore(&loongson2_wait_lock, flags);
local_irq_enable(); local_irq_enable();
} }