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MIPS: mm: Remove special handling for OCTEON CPUs 

Macro cpu_has_mips_r2_exec_hazard correctly handles OCTEON CPUs,
so we don't need the extra switch cases for them.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer 2023-06-15 11:39:33 +02:00
parent 5cad832304
commit 13e6b8122d
1 changed files with 4 additions and 20 deletions
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24
arch/mips/mm/tlbex.c
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@ -2123,16 +2123,8 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
switch (current_cpu_type()) {
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
break;
default:
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
break;
}
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {
@ -2197,16 +2189,8 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
switch (current_cpu_type()) {
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
break;
default:
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
break;
}
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {