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qcom: ipq4019: add spi node to ipq4019 SoC and DK01 device tree 

This will allow boards to enable the SPI bus

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Matthew McClintock 2016-03-23 17:05:07 -05:00 committed by Andy Gross
parent 8196dd5e5c
commit 13ad4fd36a
2 changed files with 55 additions and 0 deletions
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37
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
View File

@ -48,6 +48,43 @@
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
};
pinmux_cs {
function = "gpio";
pins = "gpio54";
};
pinconf {
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pinconf_cs {
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
spi_0: spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
cs-gpios = <&tlmm 54 0>;
mx25l25635e@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "mx25l25635e";
spi-max-frequency = <24000000>;
};
};
serial@78af000 {

18
arch/arm/boot/dts/qcom-ipq4019.dtsi
View File

@ -15,12 +15,18 @@
#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ4019";
compatible = "qcom,ipq4019";
interrupt-parent = <&intc>;
aliases {
spi0 = &spi_0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -108,6 +114,18 @@
interrupts = <0 208 0>;
};
spi_0: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
acc0: clock-controller@b088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;