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clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly 

The code was setting the bit 21 of the CPCCR register to use a divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.

This is the opposite of how this register field works: a cleared bit
means that the /2 divider is used, and a set bit means that the divider
is 1.

Restore the correct behaviour using the newly introduced .div_table
field.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Paul Cercueil 2019-05-02 23:25:02 +02:00 committed by Stephen Boyd
parent 74054c413a
commit 13ad1948d9
1 changed files with 8 additions and 1 deletions
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9
drivers/clk/ingenic/jz4725b-cgu.c
View File

@ -37,6 +37,10 @@ static const u8 jz4725b_cgu_cpccr_div_table[] = {
1, 2, 3, 4, 6, 8,
};
static const u8 jz4725b_cgu_pll_half_div_table[] = {
2, 1,
};
static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
/* External clocks */
@ -70,7 +74,10 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
[JZ4725B_CLK_PLL_HALF] = {
"pll half", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
jz4725b_cgu_pll_half_div_table,
},
},
[JZ4725B_CLK_CCLK] = {