spi: rockchip: Support 64-location deep FIFOs
The FIFO depth of SPI V2 is 64 instead of 32, add support for it. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Tested-by: Emil Renner Berthing <kernel@esmil.dk> Reviewed-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20200723004356.6390-2-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -39,8 +39,9 @@
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#define ROCKCHIP_SPI_RISR 0x0034
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#define ROCKCHIP_SPI_ICR 0x0038
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#define ROCKCHIP_SPI_DMACR 0x003c
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#define ROCKCHIP_SPI_DMATDLR 0x0040
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#define ROCKCHIP_SPI_DMARDLR 0x0044
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#define ROCKCHIP_SPI_DMATDLR 0x0040
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#define ROCKCHIP_SPI_DMARDLR 0x0044
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#define ROCKCHIP_SPI_VERSION 0x0048
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#define ROCKCHIP_SPI_TXDR 0x0400
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#define ROCKCHIP_SPI_RXDR 0x0800
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@ -156,6 +157,8 @@
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#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
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#define ROCKCHIP_SPI_MAX_CS_NUM 2
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#define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
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#define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
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struct rockchip_spi {
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struct device *dev;
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@ -206,17 +209,17 @@ static inline void wait_for_idle(struct rockchip_spi *rs)
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static u32 get_fifo_len(struct rockchip_spi *rs)
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{
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u32 fifo;
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u32 ver;
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for (fifo = 2; fifo < 32; fifo++) {
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writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
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if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
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break;
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ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
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switch (ver) {
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case ROCKCHIP_SPI_VER2_TYPE1:
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case ROCKCHIP_SPI_VER2_TYPE2:
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return 64;
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default:
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return 32;
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}
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writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
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return (fifo == 31) ? 0 : fifo;
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}
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static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
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