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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin:
  Blackfin: debug-mmrs: include RSI_PID[4567] MMRs
  Blackfin: bf51x: fix up RSI_PID# MMR defines
  Blackfin: bf52x/bf54x: fix up usb MMR defines
  Blackfin: debug-mmrs: fix typos with gptimers/mdma/ppi
  Blackfin: gptimers: add structure for hardware register layout
  Blackfin: wire up new sendmmsg syscall
  Blackfin: mach/bfin_serial_5xx.h: punt now-unused header
  Blackfin: bfin_serial.h: turn default port wrappers into stubs
This commit is contained in:
Linus Torvalds 2011-05-28 23:12:28 -07:00
parent 5be7ef0024 c320afe965
commit 139f37f5e1
15 changed files with 62 additions and 569 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/blackfin/include/asm/bfin_serial.h
View File

@ -184,7 +184,7 @@ struct bfin_uart_regs {
#undef __BFP #undef __BFP
#ifndef port_membase #ifndef port_membase
# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase) # define port_membase(p) 0
#endif #endif
#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR) #define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
@ -235,10 +235,10 @@ struct bfin_uart_regs {
#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0) #define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
#ifndef put_lsr_cache #ifndef put_lsr_cache
# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v)) # define put_lsr_cache(p, v)
#endif #endif
#ifndef get_lsr_cache #ifndef get_lsr_cache
# define get_lsr_cache(p) (((struct bfin_serial_port *)(p))->lsr) # define get_lsr_cache(p) 0
#endif #endif
/* The hardware clears the LSR bits upon read, so we need to cache /* The hardware clears the LSR bits upon read, so we need to cache

18
arch/blackfin/include/asm/gptimers.h
View File

@ -193,4 +193,22 @@ uint16_t get_enabled_gptimers(void);
uint32_t get_gptimer_status(unsigned int group); uint32_t get_gptimer_status(unsigned int group);
void set_gptimer_status(unsigned int group, uint32_t value); void set_gptimer_status(unsigned int group, uint32_t value);
/*
* All Blackfin system MMRs are padded to 32bits even if the register
* itself is only 16bits. So use a helper macro to streamline this.
*/
#define __BFP(m) u16 m; u16 __pad_##m
/*
* bfin timer registers layout
*/
struct bfin_gptimer_regs {
__BFP(config);
u32 counter;
u32 period;
u32 width;
};
#undef __BFP
#endif #endif

3
arch/blackfin/include/asm/unistd.h
View File

@ -398,8 +398,9 @@
#define __NR_clock_adjtime 377 #define __NR_clock_adjtime 377
#define __NR_syncfs 378 #define __NR_syncfs 378
#define __NR_setns 379 #define __NR_setns 379
#define __NR_sendmmsg 380
#define __NR_syscall 380 #define __NR_syscall 381
#define NR_syscalls __NR_syscall #define NR_syscalls __NR_syscall
/* Old optional stuff no one actually uses */ /* Old optional stuff no one actually uses */

36
arch/blackfin/kernel/debug-mmrs.c
View File

@ -13,6 +13,7 @@
#include <asm/blackfin.h> #include <asm/blackfin.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/gptimers.h>
#include <asm/bfin_can.h> #include <asm/bfin_can.h>
#include <asm/bfin_dma.h> #include <asm/bfin_dma.h>
#include <asm/bfin_ppi.h> #include <asm/bfin_ppi.h>
@ -230,8 +231,8 @@ bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdm
#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "") #define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
#define _MDMA(num, x) \ #define _MDMA(num, x) \
do { \ do { \
_DMA(num, x##DMA_D##num##_CONFIG, 'D', #x); \ _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
_DMA(num, x##DMA_S##num##_CONFIG, 'S', #x); \ _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
} while (0) } while (0)
#define MDMA(num) _MDMA(num, M) #define MDMA(num) _MDMA(num, M)
#define IMDMA(num) _MDMA(num, IM) #define IMDMA(num) _MDMA(num, IM)
@ -264,20 +265,15 @@ bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
/* /*
* General Purpose Timers * General Purpose Timers
*/ */
#define GPTIMER_OFF(mmr) (TIMER0_##mmr - TIMER0_CONFIG) #define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
#define __GPTIMER(name) \
do { \
strcpy(_buf, #name); \
debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, (u16 *)(base + GPTIMER_OFF(name))); \
} while (0)
static void __init __maybe_unused static void __init __maybe_unused
bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num) bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
{ {
char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num); char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
__GPTIMER(CONFIG); __GPTIMER(CONFIG, config);
__GPTIMER(COUNTER); __GPTIMER(COUNTER, counter);
__GPTIMER(PERIOD); __GPTIMER(PERIOD, period);
__GPTIMER(WIDTH); __GPTIMER(WIDTH, width);
} }
#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num) #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
@ -355,7 +351,7 @@ bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
__PPI(DELAY, delay); __PPI(DELAY, delay);
__PPI(FRAME, frame); __PPI(FRAME, frame);
} }
#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_STATUS, num) #define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
/* /*
* SPI * SPI
@ -1288,15 +1284,15 @@ static int __init bfin_debug_mmrs_init(void)
D16(VR_CTL); D16(VR_CTL);
D32(CHIPID); /* it's part of this hardware block */ D32(CHIPID); /* it's part of this hardware block */
#if defined(PPI_STATUS) || defined(PPI0_STATUS) || defined(PPI1_STATUS) #if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
parent = debugfs_create_dir("ppi", top); parent = debugfs_create_dir("ppi", top);
# ifdef PPI_STATUS # ifdef PPI_CONTROL
bfin_debug_mmrs_ppi(parent, PPI_STATUS, -1); bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
# endif # endif
# ifdef PPI0_STATUS # ifdef PPI0_CONTROL
PPI(0); PPI(0);
# endif # endif
# ifdef PPI1_STATUS # ifdef PPI1_CONTROL
PPI(1); PPI(1);
# endif # endif
#endif #endif
@ -1341,6 +1337,10 @@ static int __init bfin_debug_mmrs_init(void)
D16(RSI_PID1); D16(RSI_PID1);
D16(RSI_PID2); D16(RSI_PID2);
D16(RSI_PID3); D16(RSI_PID3);
D16(RSI_PID4);
D16(RSI_PID5);
D16(RSI_PID6);
D16(RSI_PID7);
D16(RSI_PWR_CONTROL); D16(RSI_PWR_CONTROL);
D16(RSI_RD_WAIT_EN); D16(RSI_RD_WAIT_EN);
D32(RSI_RESPONSE0); D32(RSI_RESPONSE0);

79
arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
View File

@ -1,79 +0,0 @@
/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#include <asm/dma.h>
#include <asm/portmux.h>
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
# define CONFIG_UART0_CTS_PIN -1
# endif
# ifndef CONFIG_UART0_RTS_PIN
# define CONFIG_UART0_RTS_PIN -1
# endif
# ifndef CONFIG_UART1_CTS_PIN
# define CONFIG_UART1_CTS_PIN -1
# endif
# ifndef CONFIG_UART1_RTS_PIN
# define CONFIG_UART1_RTS_PIN -1
# endif
#endif
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
int uart_status_irq;
#ifdef CONFIG_SERIAL_BFIN_DMA
unsigned int uart_tx_dma_channel;
unsigned int uart_rx_dma_channel;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
int uart_cts_pin;
int uart_rts_pin;
#endif
};
struct bfin_serial_res bfin_serial_resource[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
{
0xFFC00400,
IRQ_UART0_RX,
IRQ_UART0_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART0_TX,
CH_UART0_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
CONFIG_UART0_CTS_PIN,
CONFIG_UART0_RTS_PIN,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
{
0xFFC02000,
IRQ_UART1_RX,
IRQ_UART1_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART1_TX,
CH_UART1_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
CONFIG_UART1_CTS_PIN,
CONFIG_UART1_RTS_PIN,
#endif
},
#endif
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

16
arch/blackfin/mach-bf518/include/mach/defBF514.h
View File

@ -36,13 +36,13 @@
#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ #define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ #define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ #define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ #define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ #define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */
#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ #define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */
#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ #define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */
#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ #define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */
#endif /* _DEF_BF514_H */ #endif /* _DEF_BF514_H */

79
arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
View File

@ -1,79 +0,0 @@
/*
* Copyright 2007-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#include <asm/dma.h>
#include <asm/portmux.h>
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
# define CONFIG_UART0_CTS_PIN -1
# endif
# ifndef CONFIG_UART0_RTS_PIN
# define CONFIG_UART0_RTS_PIN -1
# endif
# ifndef CONFIG_UART1_CTS_PIN
# define CONFIG_UART1_CTS_PIN -1
# endif
# ifndef CONFIG_UART1_RTS_PIN
# define CONFIG_UART1_RTS_PIN -1
# endif
#endif
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
int uart_status_irq;
#ifdef CONFIG_SERIAL_BFIN_DMA
unsigned int uart_tx_dma_channel;
unsigned int uart_rx_dma_channel;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
int uart_cts_pin;
int uart_rts_pin;
#endif
};
struct bfin_serial_res bfin_serial_resource[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
{
0xFFC00400,
IRQ_UART0_RX,
IRQ_UART0_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART0_TX,
CH_UART0_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
CONFIG_UART0_CTS_PIN,
CONFIG_UART0_RTS_PIN,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
{
0xFFC02000,
IRQ_UART1_RX,
IRQ_UART1_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART1_TX,
CH_UART1_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
CONFIG_UART1_CTS_PIN,
CONFIG_UART1_RTS_PIN,
#endif
},
#endif
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

4
arch/blackfin/mach-bf527/include/mach/defBF525.h
View File

@ -185,8 +185,8 @@
#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ #define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ #define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ #define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ #define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ #define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ #define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */

52
arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
View File

@ -1,52 +0,0 @@
/*
* Copyright 2006-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#include <asm/dma.h>
#include <asm/portmux.h>
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
# define CONFIG_UART0_CTS_PIN -1
# endif
# ifndef CONFIG_UART0_RTS_PIN
# define CONFIG_UART0_RTS_PIN -1
# endif
#endif
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
int uart_status_irq;
#ifdef CONFIG_SERIAL_BFIN_DMA
unsigned int uart_tx_dma_channel;
unsigned int uart_rx_dma_channel;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
int uart_cts_pin;
int uart_rts_pin;
#endif
};
struct bfin_serial_res bfin_serial_resource[] = {
{
0xFFC00400,
IRQ_UART0_RX,
IRQ_UART0_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART0_TX,
CH_UART0_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
CONFIG_UART0_CTS_PIN,
CONFIG_UART0_RTS_PIN,
#endif
}
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

79
arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
View File

@ -1,79 +0,0 @@
/*
* Copyright 2006-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#include <asm/dma.h>
#include <asm/portmux.h>
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
# define CONFIG_UART0_CTS_PIN -1
# endif
# ifndef CONFIG_UART0_RTS_PIN
# define CONFIG_UART0_RTS_PIN -1
# endif
# ifndef CONFIG_UART1_CTS_PIN
# define CONFIG_UART1_CTS_PIN -1
# endif
# ifndef CONFIG_UART1_RTS_PIN
# define CONFIG_UART1_RTS_PIN -1
# endif
#endif
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
int uart_status_irq;
#ifdef CONFIG_SERIAL_BFIN_DMA
unsigned int uart_tx_dma_channel;
unsigned int uart_rx_dma_channel;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
int uart_cts_pin;
int uart_rts_pin;
#endif
};
struct bfin_serial_res bfin_serial_resource[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
{
0xFFC00400,
IRQ_UART0_RX,
IRQ_UART0_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART0_TX,
CH_UART0_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
CONFIG_UART0_CTS_PIN,
CONFIG_UART0_RTS_PIN,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
{
0xFFC02000,
IRQ_UART1_RX,
IRQ_UART1_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART1_TX,
CH_UART1_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
CONFIG_UART1_CTS_PIN,
CONFIG_UART1_RTS_PIN,
#endif
},
#endif
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

93
arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
View File

@ -1,93 +0,0 @@
/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <asm/dma.h>
#include <asm/portmux.h>
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
# define CONFIG_UART0_CTS_PIN -1
# endif
# ifndef CONFIG_UART0_RTS_PIN
# define CONFIG_UART0_RTS_PIN -1
# endif
# ifndef CONFIG_UART1_CTS_PIN
# define CONFIG_UART1_CTS_PIN -1
# endif
# ifndef CONFIG_UART1_RTS_PIN
# define CONFIG_UART1_RTS_PIN -1
# endif
#endif
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
int uart_status_irq;
#ifdef CONFIG_SERIAL_BFIN_DMA
unsigned int uart_tx_dma_channel;
unsigned int uart_rx_dma_channel;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
int uart_cts_pin;
int uart_rts_pin;
#endif
};
struct bfin_serial_res bfin_serial_resource[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
{
0xFFC00400,
IRQ_UART0_RX,
IRQ_UART0_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART0_TX,
CH_UART0_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
CONFIG_UART0_CTS_PIN,
CONFIG_UART0_RTS_PIN,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
{
0xFFC02000,
IRQ_UART1_RX,
IRQ_UART1_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART1_TX,
CH_UART1_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
CONFIG_UART1_CTS_PIN,
CONFIG_UART1_RTS_PIN,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART2
{
0xFFC02100,
IRQ_UART2_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART2_TX,
CH_UART2_RX,
#endif
#ifdef CONFIG_BFIN_UART2_CTSRTS
CONFIG_UART2_CTS_PIN,
CONFIG_UART2_RTS_PIN,
#endif
},
#endif
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

94
arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
View File

@ -1,94 +0,0 @@
/*
* Copyright 2007-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <asm/dma.h>
#include <asm/portmux.h>
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
#endif
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
int uart_status_irq;
#ifdef CONFIG_SERIAL_BFIN_DMA
unsigned int uart_tx_dma_channel;
unsigned int uart_rx_dma_channel;
#endif
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
int uart_cts_pin;
int uart_rts_pin;
#endif
};
struct bfin_serial_res bfin_serial_resource[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
{
0xFFC00400,
IRQ_UART0_RX,
IRQ_UART0_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART0_TX,
CH_UART0_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
0,
0,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
{
0xFFC02000,
IRQ_UART1_RX,
IRQ_UART1_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART1_TX,
CH_UART1_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
GPIO_PE10,
GPIO_PE9,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART2
{
0xFFC02100,
IRQ_UART2_RX,
IRQ_UART2_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART2_TX,
CH_UART2_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
0,
0,
#endif
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART3
{
0xFFC03100,
IRQ_UART3_RX,
IRQ_UART3_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART3_TX,
CH_UART3_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
GPIO_PB3,
GPIO_PB2,
#endif
},
#endif
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

19
arch/blackfin/mach-bf548/include/mach/defBF547.h
View File

@ -271,10 +271,10 @@
#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ #define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ #define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ #define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
/* USB Endpoint 1 Control Registers */ /* USB Endpoint 1 Control Registers */
#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ #define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ #define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ #define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
@ -284,10 +284,10 @@
#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ #define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ #define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ #define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
/* USB Endpoint 2 Control Registers */ /* USB Endpoint 2 Control Registers */
#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ #define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ #define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ #define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
@ -297,10 +297,10 @@
#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ #define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ #define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ #define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
/* USB Endpoint 3 Control Registers */ /* USB Endpoint 3 Control Registers */
#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ #define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ #define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ #define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
@ -310,10 +310,10 @@
#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ #define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ #define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ #define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
/* USB Endpoint 4 Control Registers */ /* USB Endpoint 4 Control Registers */
#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ #define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ #define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ #define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
@ -323,10 +323,10 @@
#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ #define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ #define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ #define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
/* USB Endpoint 5 Control Registers */ /* USB Endpoint 5 Control Registers */
#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ #define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ #define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ #define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
@ -336,10 +336,10 @@
#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ #define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ #define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ #define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
/* USB Endpoint 6 Control Registers */ /* USB Endpoint 6 Control Registers */
#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ #define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ #define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ #define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
@ -349,10 +349,10 @@
#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ #define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ #define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ #define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
/* USB Endpoint 7 Control Registers */ /* USB Endpoint 7 Control Registers */
#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ #define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ #define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ #define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
@ -361,8 +361,9 @@
#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ #define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ #define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ #define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ #define USB_EP_NI7_RXINTERVAL 0xffc03fe0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ #define USB_EP_NI7_TXCOUNT 0xffc03fe8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ #define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
/* USB Channel 0 Config Registers */ /* USB Channel 0 Config Registers */

52
arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
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@ -1,52 +0,0 @@
/*
* Copyright 2006-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <asm/dma.h>
#include <asm/portmux.h>
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
# define CONFIG_UART0_CTS_PIN -1
# endif
# ifndef CONFIG_UART0_RTS_PIN
# define CONFIG_UART0_RTS_PIN -1
# endif
#endif
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
int uart_status_irq;
#ifdef CONFIG_SERIAL_BFIN_DMA
unsigned int uart_tx_dma_channel;
unsigned int uart_rx_dma_channel;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
int uart_cts_pin;
int uart_rts_pin;
#endif
};
struct bfin_serial_res bfin_serial_resource[] = {
{
0xFFC00400,
IRQ_UART_RX,
IRQ_UART_ERROR,
#ifdef CONFIG_SERIAL_BFIN_DMA
CH_UART_TX,
CH_UART_RX,
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
CONFIG_UART0_CTS_PIN,
CONFIG_UART0_RTS_PIN,
#endif
}
};
#define DRIVER_NAME "bfin-uart"
#include <asm/bfin_serial.h>

1
arch/blackfin/mach-common/entry.S
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@ -1754,6 +1754,7 @@ ENTRY(_sys_call_table)
.long _sys_clock_adjtime .long _sys_clock_adjtime
.long _sys_syncfs .long _sys_syncfs
.long _sys_setns .long _sys_setns
.long _sys_sendmmsg /* 380 */
.rept NR_syscalls-(.-_sys_call_table)/4 .rept NR_syscalls-(.-_sys_call_table)/4
.long _sys_ni_syscall .long _sys_ni_syscall